Cypress ISR 37000 CPLD User Manual

5V, 3.3V, ISR™ High-Performance CPLDsUltra37000 CPLD FamilyCypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 10 of 64Logic Block Diagrams (continued)TDITCKTMSTDOJTAG TapControllerCY37128/CY37128V PIMINP

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 11 of 64Logic Block Diagrams (continued)CY37256/CY37256V LOGICBLOCKGLOGICBLOCKHLOGICBLOCKILOG

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 12 of 64Logic Block Diagrams (continued)CY37384/CY37384V LOGICBLOCKAHLOGICBLOCKAILOGICBLOCKBD

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 13 of 64Logic Block Diagrams (continued)CY37512/CY37512VLOGICBLOCKAGLOGICBLOCKAHLOGICBLOCKBIL

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 14 of 645.0V Device CharacteristicsMaximum Ratings(Above which the useful life may be impaire

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 15 of 643.3V Device CharacteristicsMaximum Ratings(Above which the useful life may be impaire

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 16 of 64 Inductance[5]Parameter Description Test Conditions44- LeadTQFP44- LeadPLCC44- LeadCL

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 17 of 64Parameter[11]VXOutput Waveform—Measurement LeveltER(–)1.5VtER(+)2.6VtEA(+)1.5VtEA(–)V

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 18 of 64Product Term Clocking ParameterstCOPT[13, 14, 15]Product Term Clock or Latch Enable (

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 19 of 64Switching Characteristics Over the Operating Range[12]Parameter200 MHz 167 MHz154 MHz

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 2 of 64Selection Guide5.0V Selection Guide General InformationDevice Macrocells Dedicated Inp

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 20 of 64tRO[13, 14, 15]12 13 13 14 15 18 21 26 nstPW8 8 8 8 10 12 15 20 nstPR[13]10 10 10 10

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 21 of 64Registered Output with Product Term Clocking Input Going Through the ArrayRegistered

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 22 of 64Registered InputClock to ClockLatched InputSwitching Waveforms (continued)tISREGISTER

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 23 of 64Latched Input and OutputAsynchronous ResetAsynchronous PresetOutput Enable/DisableSwi

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 24 of 64Power ConsumptionTypical 5.0V Power ConsumptionCY37032CY3706401020304050600 50 100 15

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 25 of 64CY37128CY37192Typical 5.0V Power Consumption (continued)0204060801001201401600 20 40

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 26 of 64CY37256CY37384Typical 5.0V Power Consumption (continued)0501001502002503000 20 40 60

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 27 of 64CY37512Typical 5.0V Power Consumption (continued)01002003004005006000 20 40 60 80 100

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 28 of 64CY37064VCY37128VTypical 3.3V Power Consumption (continued)0510152025303540450 20 40 6

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 29 of 64CY37192VCY37256VTypical 3.3V Power Consumption (continued)0204060801001200 20 40 60 8

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 3 of 64 Architecture Overview of Ultra37000 FamilyProgrammable Interconnect MatrixThe PIM con

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 30 of 64CY37384VCY37512VTypical 3.3V Power Consumption (continued)020406080100120140160180200

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 31 of 64Pin Configurations[20]44-pin TQFP (A44)Top ViewI/O2GNDVCCOI/O3I/O4I/O1I/O0I/O29I/O30I

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 32 of 64Note: 20. For 3.3V versions (Ultra37000V), VCCO = VCC.Note: 21. This pin is a N/C, bu

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 33 of 64Pin Configurations[20] (continued)Top View100-lead TQFP (A100)100 9798 96231424159606

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 34 of 64Pin Configurations[20] (continued)100-ball Fine-Pitch BGA (BB100) for CY37064VTop Vie

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 35 of 64Pin Configurations[20] (continued)I/O771241231221211201191181171161151141131121111101

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 36 of 64Pin Configurations[20] (continued)I/O721241231221211201191181171161151141131121111101

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 37 of 64Pin Configurations[20] (continued)I/O152I/O154I/O153234567891011121314151617181920212

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 38 of 64Pin Configurations[20] (continued)292-Ball PBGA (BG292)Top View1 2 3 4 5 6 7 8 9 1011

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 39 of 64Pin Configurations[20] (continued)256-Ball Fine-Pitch BGA (BB256)Top View123456789101

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 4 of 64Low-Power OptionEach logic block can operate in high-speed mode for criticalpath perfo

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 40 of 64Pin Configurations[20] (continued)388-Lead PBGA (BG388)Top View1234567891011121314151

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 41 of 64Pin Configurations[20] (continued)400-Ball Fine-Pitch BGA (BB400)Top ViewA GND GND NC

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 42 of 64Ordering Information5.0V Ordering InformationMacrocells Speed(MHz) Ordering CodePacka

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 43 of 6464 154 CY37064P44-154AC A44 44-Lead Thin Quad Flat Pack CommercialCY37064P44-154JC J6

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 44 of 64128 167 CY37128P84-167JC J83 84-Lead Plastic Leaded Chip Carrier CommercialCY37128P84

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 45 of 64256 154 CY37256P160-154AC A160 160-Lead Thin Quad Flat Pack CommercialCY37256P160-154

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 46 of 64512 125 CY37512P208-125NC N208 208-Lead Plastic Quad Flat Pack CommercialCY37512P256-

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 47 of 6464 143 CY37064VP44-143AC A44 44-Lead Thin Quad Flatpack CommercialCY37064VP44-143AXC

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 48 of 64256 100 CY37256VP160-100AC A160 160-Lead Thin Quad Flat Pack CommercialCY37256VP160-1

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 49 of 64Package Diagrams51-85064-*B44-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack A4451-8

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 5 of 64The buried macrocell also supports input register capability.The buried macrocell can

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 50 of 64Package Diagrams (continued)44-Lead Ceramic Leaded Chip Carrier Y6751-80014-**[+] Fee

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 51 of 64Package Diagrams (continued)48-Ball (7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch) Thin BGA B

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 52 of 64Package Diagrams (continued)84-Lead Ceramic Leaded Chip Carrier Y8451-80095-*A[+] Fee

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 53 of 64Package Diagrams (continued)51-85048-*B100-Lead Lead (Pb)-Free Thin Plastic Quad Flat

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 54 of 64Package Diagrams (continued)100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB10051-

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 55 of 64Package Diagrams (continued)51-85049-*B160-Lead Lead (Pb)-Free Thin Plastic Quad Flat

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 56 of 64Package Diagrams (continued)SEATING PLANEDIMENSION IN MM (INCH)2.79(.110)2.03(.080)0.

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 57 of 64Package Diagrams (continued)208-Lead Plastic Quad Flatpack N20851-85069-*B[+] Feedbac

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 58 of 64Package Diagrams (continued)SEATING PLANEDIMENSIONS IN MM (INCH)0.500(.020)0.050(.002

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 59 of 64Package Diagrams (continued)BOTTOM VIEWTOP VIEW10987654321ABCDEFGHJKPIN 1 CORNERPIN 1

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 6 of 64ClockingEach I/O and buried macrocell has access to four synchronousclocks (CLK0, CLK1

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 60 of 64Package Diagrams (continued)292-Ball Plastic Ball Grid Array PBGA (27 x 27 x 2.33 mm)

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 61 of 64Package Diagrams (continued)51-85103-*C388-Ball Plastic Ball Grid Array PBGA (35 x 35

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 62 of 64© Cypress Semiconductor Corporation, 2005. The information contained herein is subjec

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 63 of 64Addendum3.3V Operating Range (CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-14

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 64 of 64Document History PageDocument Title: Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Perfo

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 7 of 64JTAG and PCI StandardsPCI Compliance5V operation of the Ultra37000 is fully compliant

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 8 of 64The third programming option for Ultra37000 devices is toutilize the embedded controll

Ultra37000 CPLD FamilyDocument #: 38-03007 Rev. *E Page 9 of 64Logic Block DiagramsCY37032/CY37032VLOGICBLOCKBLOGICBLOCKA36163616InputClock/Input16 I