Cypress NoBL CY7C1370DV25 User Manual

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18-Mbit (512K x 36/1M x 18)
Pipelined SRAM with NoBL™ Architecture
CY7C1370DV25
CY7C1372DV25
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-05558 Rev. *D Revised June 29, 2006
Features
Pin-compatible and functionally equivalent to ZBT™
Supports 250-MHz bus operations with zero wait states
Available speed grades are 250, 200 and 167 MHz
Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
Fully registered (inputs and outputs) for pipelined
operation
Byte Write capability
Single 2.5V core power supply (V
DD
)
2.5V I/O power supply (V
DDQ
)
Fast clock-to-output times
2.6 ns (for 250-MHz device)
Clock Enable (CEN
) pin to suspend operation
Synchronous self-timed writes
Available in JEDEC-standard lead-free 100-Pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165-Ball
FBGA packages
IEEE 1149.1 JTAG-Compatible Boundary Scan
Burst capability—linear or interleaved burst order
“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x
36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1370DV25 and
CY7C1372DV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1370DV25
and CY7C1372DV25 are pin-compatible and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
a
–BW
d
for CY7C1370DV25 and BW
a
–BW
b
for
CY7C1372DV25) and a Write Enable (WE
) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE
) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
DQP
c
DQP
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
C
EN
WRITE
DRIVERS
BW
c
BW
d
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block Diagram-CY7C1370DV25 (512K x 36)
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Summary of Contents

Page 1 - CY7C1372DV25

18-Mbit (512K x 36/1M x 18)Pipelined SRAM with NoBL™ ArchitectureCY7C1370DV25CY7C1372DV25Cypress Semiconductor Corporation • 198 Champion Court • San

Page 2

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 10 of 27IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1370DV25/CY7C1372DV25 incorporates

Page 3

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 11 of 27TAP RegistersRegisters are connected between the TDI and TDO balls andallow data t

Page 4

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 12 of 27BYPASSWhen the BYPASS instruction is loaded in the instructionregister and the TAP

Page 5

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 13 of 27TAP AC Switching Characteristics Over the Operating Range[9, 10]Parameter Descript

Page 6

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 14 of 272.5V TAP AC Test ConditionsInput pulse levels ...

Page 7

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 15 of 27Identification CodesInstruction Code DescriptionEXTEST 000 Captures I/O ring conte

Page 8

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 16 of 27165-Ball FBGA Boundary Scan Order[12, 14]Bit # Ball ID Bit # Ball ID Bit # Ball ID

Page 9

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 17 of 27Maximum Ratings (Above which the useful life may be impaired. For user guide-lines

Page 10 - [+] Feedback

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 18 of 27Capacitance[17]Parameter Description Test Conditions100 TQFPPackage119 BGAPackage1

Page 11

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 19 of 27Switching Characteristics Over the Operating Range [22, 23]Parameter Description–2

Page 12

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 2 of 27A0, A1, ACMODEBWaBWbWECE1CE2CE3OEREAD LOGICDQsDQPaDQPbDATASTEERINGOUTPUTBUFFERSMEMO

Page 13

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 20 of 27Switching WaveformsRead/Write/Timing[24, 25, 26]Notes: 24. For this waveform ZZ is

Page 14

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 21 of 27Notes: 27. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being us

Page 15 - 13. Bit# 85 is pre-set HIGH

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 22 of 27Ordering InformationNot all of the speed, package and temperature ranges are avail

Page 16 - 14. Bit# 89 is pre-set HIGH

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 23 of 27250 CY7C1370DV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Le

Page 17

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 24 of 27Package Diagrams NOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DOES NOT INC

Page 18

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 25 of 27Package Diagrams (continued)51-85115-*B119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

Page 19

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 26 of 27© Cypress Semiconductor Corporation, 2006. The information contained herein is sub

Page 20

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 27 of 27Document History PageDocument Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512K x 36/

Page 21

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 3 of 27Pin ConfigurationsAAAAA1A0VSSVDDAAAAAAVDDQVSSDQb DQb DQb VSSVDDQDQb DQb VSSNC VDDDQ

Page 22

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 4 of 27Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUDQaVDDQNC/576MNC/1GDQcDQdDQcD

Page 23

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 5 of 27Pin Configurations (continued)234 5671ABCDEFGHJKLMNPRTDONC/576MNC/1GDQPcDQcDQPdNCDQ

Page 24

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 6 of 27Pin DefinitionsPin Name I/O Type Pin DescriptionA0A1AInput-SynchronousAddress Input

Page 25

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 7 of 27IntroductionFunctional OverviewThe CY7C1370DV25 and CY7C1372DV25 aresynchronous-pip

Page 26

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 8 of 27signals. The CY7C1370DV25/CY7C1372DV25 provides bytewrite capability that is descri

Page 27

CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 9 of 27Truth Table[1, 2, 3, 4, 5, 6, 7]OperationAddress Used CE ZZ ADV/LD WE BWxOE CEN CLK

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