18-Mbit (512K x 36/1M x 18)Pipelined SRAM with NoBL™ ArchitectureCY7C1370DV25CY7C1372DV25Cypress Semiconductor Corporation • 198 Champion Court • San
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 10 of 27IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1370DV25/CY7C1372DV25 incorporates
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 11 of 27TAP RegistersRegisters are connected between the TDI and TDO balls andallow data t
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 12 of 27BYPASSWhen the BYPASS instruction is loaded in the instructionregister and the TAP
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 13 of 27TAP AC Switching Characteristics Over the Operating Range[9, 10]Parameter Descript
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 14 of 272.5V TAP AC Test ConditionsInput pulse levels ...
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 15 of 27Identification CodesInstruction Code DescriptionEXTEST 000 Captures I/O ring conte
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 16 of 27165-Ball FBGA Boundary Scan Order[12, 14]Bit # Ball ID Bit # Ball ID Bit # Ball ID
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 17 of 27Maximum Ratings (Above which the useful life may be impaired. For user guide-lines
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 18 of 27Capacitance[17]Parameter Description Test Conditions100 TQFPPackage119 BGAPackage1
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 19 of 27Switching Characteristics Over the Operating Range [22, 23]Parameter Description–2
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 2 of 27A0, A1, ACMODEBWaBWbWECE1CE2CE3OEREAD LOGICDQsDQPaDQPbDATASTEERINGOUTPUTBUFFERSMEMO
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 20 of 27Switching WaveformsRead/Write/Timing[24, 25, 26]Notes: 24. For this waveform ZZ is
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 21 of 27Notes: 27. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being us
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 22 of 27Ordering InformationNot all of the speed, package and temperature ranges are avail
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 23 of 27250 CY7C1370DV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Le
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 24 of 27Package Diagrams NOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DOES NOT INC
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 25 of 27Package Diagrams (continued)51-85115-*B119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 26 of 27© Cypress Semiconductor Corporation, 2006. The information contained herein is sub
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 27 of 27Document History PageDocument Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512K x 36/
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 3 of 27Pin ConfigurationsAAAAA1A0VSSVDDAAAAAAVDDQVSSDQb DQb DQb VSSVDDQDQb DQb VSSNC VDDDQ
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 4 of 27Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUDQaVDDQNC/576MNC/1GDQcDQdDQcD
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 5 of 27Pin Configurations (continued)234 5671ABCDEFGHJKLMNPRTDONC/576MNC/1GDQPcDQcDQPdNCDQ
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 6 of 27Pin DefinitionsPin Name I/O Type Pin DescriptionA0A1AInput-SynchronousAddress Input
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 7 of 27IntroductionFunctional OverviewThe CY7C1370DV25 and CY7C1372DV25 aresynchronous-pip
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 8 of 27signals. The CY7C1370DV25/CY7C1372DV25 provides bytewrite capability that is descri
CY7C1370DV25CY7C1372DV25Document #: 38-05558 Rev. *D Page 9 of 27Truth Table[1, 2, 3, 4, 5, 6, 7]OperationAddress Used CE ZZ ADV/LD WE BWxOE CEN CLK
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