Cypress NoBL CY7C1470V33 User Manual

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72-Mbit (2M x 36/4M x 18/1M x 72)
Pi
p
elined SRAM with NoBL™ Architecture
CY7C1470V33
CY7C1472V33
CY7C1474V33
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-05289 Rev. *I Revised June 20, 2006
Features
Pin-compatible and functionally equivalent to ZBT™
Supports 250-MHz bus operations with zero wait states
Available speed grades are 250, 200 and 167 MHz
Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
Fully registered (inputs and outputs) for pipelined
operation
Byte Write capability
Single 3.3V power supply
3.3V/2.5V I/O power supply
Fast clock-to-output time
3.0 ns (for 250-MHz device)
Clock Enable (CEN
) pin to suspend operation
Synchronous self-timed writes
CY7C1470V33, CY7C1472V33 available in
JEDEC-standard lead-free 100-pin TQFP, lead-free and
non-lead-free 165-ball FBGA package. CY7C1474V33
available in lead-free and non-lead-free 209 ball FBGA
package
IEEE 1149.1 JTAG Boundary Scan compatible
Burst capability—linear or interleaved burst order
“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write operations with no wait states. The
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1470V33, CY7C1472V33,
and CY7C1474V33 are pin compatible and functionally equiv-
alent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
a
–BW
h
for CY7C1474V33, BW
a
–BW
d
for CY7C1470V33
and BW
a
–BW
b
for CY7C1472V33) and a Write Enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE
) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1470V33 (2M x 36)
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
DQP
c
DQP
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
C
LK
C
EN
WRITE
DRIVERS
BW
c
BW
d
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
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Summary of Contents

Page 1 - CY7C1474V33

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ ArchitectureCY7C1470V33CY7C1472V33CY7C1474V33Cypress Semiconductor Corporation • 198 Cham

Page 2

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 10 of 29Partial Write Cycle Description[1, 2, 3, 8]Function (CY7C1470V33) WE BWdBW

Page 3

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 11 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1470V33, CY7C1472V33, and C

Page 4

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 12 of 29Instruction RegisterThree-bit instructions can be serially loaded into the

Page 5

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 13 of 29possible to capture all other signals and simply ignore thevalue of the CL

Page 6

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 14 of 293.3V TAP AC Test ConditionsInput pulse levels ...

Page 7

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 15 of 29Identification Register DefinitionsInstruction FieldCY7C1470V33(2M x 36)CY

Page 8

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 16 of 29Boundary Scan Exit Order (2M x 36)Bit # 165-Ball ID Bit # 165-Ball ID Bit

Page 9

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 17 of 29Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit

Page 10 - [+] Feedback

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 18 of 29Maximum Ratings (Above which the useful life may be impaired. For user gui

Page 11

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 19 of 29 Capacitance[15]Parameter Description Test Conditions100 TQFPMax.165 FBGAM

Page 12

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 2 of 29 A0, A1, ACMODECE1CE2CE3OEREAD LOGICDQsDQPaDQPbDQPcDQPdDQPeDQPfDQPgDQPhDAT

Page 13

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 20 of 29Switching Characteristics Over the Operating Range [16, 17]Parameter Descr

Page 14

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 21 of 29Switching Waveforms Read/Write/Timing[22, 23, 24]Notes: 22. For this wavef

Page 15

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 22 of 29NOP, STALL and DESELECT Cycles[22, 23, 25]ZZ Mode Timing[26, 27]Notes: 25.

Page 16

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 23 of 29Ordering Information Not all of the speed, package and temperature ranges

Page 17

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 24 of 29250 CY7C1470V33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4

Page 18

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 25 of 29Package Diagrams NOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DOES

Page 19

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 26 of 29Package Diagrams (continued)A1PIN 1 CORNER17.00±0.1015.00±0.107.001.00Ø0.

Page 20

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 27 of 29© Cypress Semiconductor Corporation, 2006. The information contained herei

Page 21

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 28 of 29Document History PageDocument Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 7

Page 22

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 29 of 29*H 416221 See ECN RXU Converted from Preliminary to FinalChanged address o

Page 23

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 3 of 29 Pin ConfigurationsAAAAA1A0VSSVDDAAAAAAVDDQVSSDQb DQb DQb VSSVDDQDQb DQb VS

Page 24

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 4 of 29Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTDONC/576MNC/1GDQPcDQcD

Page 25

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 5 of 29Pin Configurations (continued)ABCDEFGHJKLMNPRTUVW123456789 1110DQgDQgDQgDQg

Page 26

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 6 of 29 Pin DefinitionsPin Name I/O Type Pin DescriptionA0A1AInput-SynchronousAdd

Page 27

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 7 of 29Functional OverviewThe CY7C1470V33, CY7C1472V33, and CY7C1474V33 aresynchro

Page 28

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 8 of 29On the next clock rise the data presented to DQ and DQP(DQa,b,c,d,e,f,g,h/D

Page 29

CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 9 of 29Notes: 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands f

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