72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ ArchitectureCY7C1470V33CY7C1472V33CY7C1474V33Cypress Semiconductor Corporation • 198 Cham
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 10 of 29Partial Write Cycle Description[1, 2, 3, 8]Function (CY7C1470V33) WE BWdBW
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 11 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1470V33, CY7C1472V33, and C
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 12 of 29Instruction RegisterThree-bit instructions can be serially loaded into the
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 13 of 29possible to capture all other signals and simply ignore thevalue of the CL
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 14 of 293.3V TAP AC Test ConditionsInput pulse levels ...
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 15 of 29Identification Register DefinitionsInstruction FieldCY7C1470V33(2M x 36)CY
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 16 of 29Boundary Scan Exit Order (2M x 36)Bit # 165-Ball ID Bit # 165-Ball ID Bit
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 17 of 29Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 18 of 29Maximum Ratings (Above which the useful life may be impaired. For user gui
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 19 of 29 Capacitance[15]Parameter Description Test Conditions100 TQFPMax.165 FBGAM
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 2 of 29 A0, A1, ACMODECE1CE2CE3OEREAD LOGICDQsDQPaDQPbDQPcDQPdDQPeDQPfDQPgDQPhDAT
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 20 of 29Switching Characteristics Over the Operating Range [16, 17]Parameter Descr
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 21 of 29Switching Waveforms Read/Write/Timing[22, 23, 24]Notes: 22. For this wavef
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 22 of 29NOP, STALL and DESELECT Cycles[22, 23, 25]ZZ Mode Timing[26, 27]Notes: 25.
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 23 of 29Ordering Information Not all of the speed, package and temperature ranges
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 24 of 29250 CY7C1470V33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 25 of 29Package Diagrams NOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DOES
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 26 of 29Package Diagrams (continued)A1PIN 1 CORNER17.00±0.1015.00±0.107.001.00Ø0.
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 27 of 29© Cypress Semiconductor Corporation, 2006. The information contained herei
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 28 of 29Document History PageDocument Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 7
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 29 of 29*H 416221 See ECN RXU Converted from Preliminary to FinalChanged address o
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 3 of 29 Pin ConfigurationsAAAAA1A0VSSVDDAAAAAAVDDQVSSDQb DQb DQb VSSVDDQDQb DQb VS
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 4 of 29Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTDONC/576MNC/1GDQPcDQcD
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 5 of 29Pin Configurations (continued)ABCDEFGHJKLMNPRTUVW123456789 1110DQgDQgDQgDQg
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 6 of 29 Pin DefinitionsPin Name I/O Type Pin DescriptionA0A1AInput-SynchronousAdd
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 7 of 29Functional OverviewThe CY7C1470V33, CY7C1472V33, and CY7C1474V33 aresynchro
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 8 of 29On the next clock rise the data presented to DQ and DQP(DQa,b,c,d,e,f,g,h/D
CY7C1470V33CY7C1472V33CY7C1474V33Document #: 38-05289 Rev. *I Page 9 of 29Notes: 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands f
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