Cypress NoBL CY7C1471V25 User Manual

72-Mbit (2M x 36/4M x 18/1M x 72)Flow-Through SRAM with NoBL™ ArchitectureCY7C1471V25CY7C1473V25CY7C1475V25Cypress Semiconductor Corporation • 198 Cha

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 10 of 32Because the CY7C1471V25, CY7C1473V25, andCY7C1475V25 are common IO devices,

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 11 of 32Truth Table The truth table for CY7C1471V25, CY7C1473V25, and CY7C1475V25 f

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 12 of 32Truth Table for Read/Write The read-write truth table for CY7C1471V25 follo

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 13 of 32IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1471V25, CY7C1473V25, and CY

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 14 of 32TAP RegistersRegisters are connected between the TDI and TDO balls andenabl

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 15 of 32signal while in transition (metastable state). This does notharm the device

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 16 of 32TAP AC Switching Characteristics Over the Operating Range[10, 11]Parameter

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 17 of 321.8V TAP AC Test ConditionsInput pulse levels ...

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 18 of 32Scan Register SizesRegister Name Bit Size (x36) Bit Size (x18) Bit Size (x7

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 19 of 32Boundary Scan Exit Order (2M x 36)Bit # 165-Ball ID Bit # 165-Ball ID Bit #

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 2 of 32Logic Block Diagram – CY7C1471V25 (2M x 36)Logic Block Diagram – CY7C1473V25

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 20 of 32Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 21 of 32Maximum RatingsExceeding maximum ratings may impair the useful life of thed

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 22 of 32CapacitanceTested initially and after any design or process change that may

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 23 of 32Switching Characteristics Over the Operating Range. Timing reference level

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 24 of 32Switching WaveformsFigure 1 shows read-write timing waveform.[19, 20, 21]Fi

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 25 of 32Figure 2 shows NOP, STALL and DESELECT Cycles waveform.[19, 20, 22]Figure 2

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 26 of 32Figure 3 shows ZZ Mode timing waveform.[23, 24]Figure 3. ZZ Mode TimingSwit

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 27 of 32Ordering InformationNot all of the speed, package and temperature ranges ar

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 28 of 32Package Diagrams Figure 4. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 29 of 32Figure 5. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165Package Diagrams (cont

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 3 of 32Logic Block Diagram – CY7C1475V25 (1M x 72)A0, A1, ACMODECE1CE2CE3OEREAD LOG

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 30 of 32© Cypress Semiconductor Corporation, 2002-2007. The information contained h

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 31 of 32Document History PageDocument Title: CY7C1471V25/CY7C1473V25/CY7C1475V25, 7

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 32 of 32*H 472335 See ECN VKN Corrected the typo in the pin configuration for 209-B

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 4 of 32Pin Configurations 100-Pin TQFP PinoutAAAAA1A0NC/288MNC/144MVSSVDDAAAAAADQPB

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 5 of 32Pin Configurations (continued)100-Pin TQFP PinoutAAAAA1A0NC/288MNC/144MVSSV

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 6 of 32Pin Configurations (continued)165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 7 of 32Pin Configurations (continued)ABCDEFGHJKLMNPRTUVW12 34 5 6 78 9 1110DQgDQgD

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 8 of 32Pin DefinitionsName IO DescriptionA0, A1, A Input-SynchronousAddress Inputs

CY7C1471V25CY7C1473V25CY7C1475V25Document #: 38-05287 Rev. *I Page 9 of 32Functional OverviewThe CY7C1471V25, CY7C1473V25, and CY7C1475V25 aresynchron