Cypress Rambus XDR CY24271 User Manual

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CY24272
Rambus
®
XDR™ Clock Generator with
Zero SDA Hold Time
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-42414 Rev. ** Revised November 9, 2007
Features
Meets Rambus
®
Extended Data Rate (XDR™) clocking
requirements
25 ps typical cycle-to-cycle jitter
–135 dBc/Hz typical phase noise at 20 MHz offset
100 or 133 MHz differential clock input
300–667 MHz high speed clock support
Quad (open drain) differential output drivers
Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4
Spread Aware™
2.5V operation
28-pin TSSOP package
Table 1. Device Comparison
CY24271 CY24272
SDA hold time = 300 ns
(SMBus compliant)
SDA hold time = 0 ns
(I
2
C compliant)
R
RC
= 200Ω typical
(Rambus standard drive)
R
RC
= 295Ω minimum
(Reduced output drive)
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
CLK3
CLK3B
REFCLK,REFCLKB
SCL SDA ID0
ID1
EN
RegA
EN
RegB
EN
RegC
EN
RegD
PLL
Bypass
MUX
/BYPASS EN
Logic Block Diagram
[+] Feedback
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Summary of Contents

Page 1 - Zero SDA Hold Time

CY24272Rambus® XDR™ Clock Generator withZero SDA Hold TimeCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2

Page 2 - Pinouts

CY24272Document Number: 001-42414 Rev. ** Page 10 of 13Test and Measurement SetupFigure 3. Clock Outputs Signal WaveformsA physical signal that appea

Page 3 - Modes of Operation

CY24272Document Number: 001-42414 Rev. ** Page 11 of 13Figure 4. Input and Output Waveforms Figure 5. Crossing Point VoltageFigure 6. Cycle-to-cycl

Page 4 - SMBus Data Byte Definitions

CY24272Document Number: 001-42414 Rev. ** Page 12 of 13Package Drawing and DimensionFigure 8. 28-Pin Thin Shrunk Small Outline Package (4.40-mm Body)

Page 5

Document Number: 001-42414 Rev. ** Revised November 9, 2007 Page 13 of 13PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademark

Page 6 - Absolute Maximum Conditions

CY24272Document Number: 001-42414 Rev. ** Page 2 of 13Pinouts Table 2. Pin Definition - 28 Pin TSSOPPin No. Name IO Description1 VDDP PWR 2.5V power

Page 7 - DC Operating Conditions

CY24272Document Number: 001-42414 Rev. ** Page 3 of 13PLL MultiplierTable 3 shows the frequency multipliers in the PLL, selectable by programming the

Page 8 - DC Electrical Specifications

CY24272Document Number: 001-42414 Rev. ** Page 4 of 13Device ID and SMBus Device AddressThe device ID (ID0 and ID1) is a part of the SMBus device 8-bi

Page 9 - AC Electrical Specification

CY24272Document Number: 001-42414 Rev. ** Page 5 of 13 Note5. RW = Read and Write, RO = Read Only, POD = Power on default. See Table 3 on page 3 for

Page 10 - Signal Waveforms

CY24272Document Number: 001-42414 Rev. ** Page 6 of 13Figure 2. Differential and Single-Ended Clock InputsAbsolute Maximum ConditionsParameter Descri

Page 11 - [+] Feedback

CY24272Document Number: 001-42414 Rev. ** Page 7 of 13DC Operating ConditionsParameter Description Condition Min Max UnitVDDPSupply Voltage for PLL 2.

Page 12 - Ordering Information

CY24272Document Number: 001-42414 Rev. ** Page 8 of 13AC Operating ConditionsThe AC operating conditions follow.[6]Parameter Description Condition Min

Page 13 - Document History Page

CY24272Document Number: 001-42414 Rev. ** Page 9 of 13AC Electrical SpecificationThe AC Electrical specifications follow. [6]Parameter Description Min

Related models: Rambus XDR CY24272

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