Cypress enCoRe CY7C63310 User Manual

CY7C63310, CY7C638xxenCoRe™ IILow Speed USB Peripheral ControllerCypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 40

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 10 of 837.2.2 Source DirectThe result of an instruction using this addressing mode is placedin ei

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 11 of 837.2.6 Destination Direct Source ImmediateThe result of an instruction using this addressi

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 12 of 838. Instruction Set SummaryThe instruction set is summarized in Ta b l e 8-1 numerically a

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 13 of 839. Memory Organization9.1 Flash Program Memory OrganizationFigure 9-1. Program Memory S

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 14 of 839.2 Data Memory OrganizationThe CY7C63310/638xx microcontrollers provide up to 256 bytes

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 15 of 83Two important variables that are used for all functions are KEY1and KEY2. These variables

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 16 of 839.5.3 WriteBlock FunctionThe WriteBlock function is used to store data in the Flash. Data

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 17 of 839.5.6 EraseAll FunctionThe EraseAll function performs a series of steps that destroy theu

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 18 of 83Figure 9-3. SROM TableThe Silicon IDs for enCoRe II devices are stored in SROM tables in

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 19 of 839.5.8 Checksum FunctionThe Checksum function calculates a 16-bit checksum over auser spec

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 2 of 83Internal 24 MHz Oscillator3.3VRegulatorClockControlPOR /Low-VoltageDetectWatchdogTimerRAMUp

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 20 of 83Figure 10-1. Clock Block DiagramCPU_CLKEXT24 MHzMUXCLK_USBSEL SCALECLK_24MHzCLK_EXTCPUCLK

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 21 of 8310.1 Clock Architecture DescriptionThe enCoRe II clock selection circuitry allows the sel

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 22 of 83Table 10-2. LPOSC Trim (LPOSCTR) [0x36] [R/W] Bit # 7 6 5 4 3 2 1 0Field 32 kHz Low Power

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 23 of 83Table 10-4. OSC Control 0 (OSC_CR0) [0x1E0] [R/W] Bit # 7 6 5 4 3 2 1 0Field Reserved No

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 24 of 83Table 10-5. USB Osclock Clock Configuration (OSCLCKCR) [0x39] [R/W] Bit # 7 6 5 4 3 2 1 0

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 25 of 8310.1.1 Interval Timer Clock (ITMRCLK)The Interval Timer Clock (TITMRCLK), is sourced from

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 26 of 8310.2 CPU Clock During Sleep ModeWhen the CPU enters sleep mode the CPUCLK Select (Bit [0]

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 27 of 8311. ResetThe microcontroller supports two types of resets: Power on Reset (POR) and Watch

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 28 of 8311.1 Power on ResetPOR occurs every time the power to the device is switched on.POR is re

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 29 of 8312.1 Sleep SequenceThe SLEEP bit is an input into the sleep logic circuit. This circuitis

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 3 of 833. IntroductionCypress has reinvented its leadership position in the low speedUSB market w

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 30 of 8312.3 Low Power in Sleep ModeTo achieve the lowest possible power consumption duringsuspen

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 31 of 8313. Low Voltage Detect Control Table 13-1. Low Voltage Control Register (LVDCR) [0x1E3]

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 32 of 8313.0.1 ECO Trim RegisterTable 13-2. Voltage Monitor Comparators Register (VLTCMP) [0x1E4

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 33 of 8314. General Purpose IO (GPIO) Ports14.1 Port Data RegistersTable 14-1. P0 Data Register

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 34 of 83Table 14-2. P1 Data Register (P1DATA) [0x01] [R/W]Bit # 7 6 5 4 3 2 1 0Field P1.7 P1.6/SM

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 35 of 8314.2 GPIO Port ConfigurationAll the GPIO configuration registers have common configuratio

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 36 of 83Figure 14-1. Block Diagram of a GPIOVCCVREGVCCVREGGPIOPINRUPData OutVCC GNDVREG GND3.3V D

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 37 of 83Table 14-7. P0.2/INT0–P0.4/INT2 Configuration (P02CR–P04CR) [0x07–0x09] [R/W]Bit # 7 6 5

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 38 of 83Table 14-9. P0.7 Configuration (P07CR) [0x0C] [R/W]Bit # 7 6 5 4 3 2 1 0Field Reserved In

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 39 of 83Table 14-13. P1.3 Configuration (P13CR) [0x10] [R/W]Bit # 7 6 5 4 3 2 1 0Field Reserved I

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 4 of 835. PinoutsFigure 5-1. Pin Diagrams1234569111516171819202221NCP0.7TIO1/P0.6TIO0/P0.5INT2/P

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 40 of 8315. Serial Peripheral Interface (SPI)The SPI Master/Slave Interface core logic runs on th

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 41 of 8315.2 SPI Configure Register Table 15-2. SPI Configure Register (SPICR) [0x3D] [R/W]Bit #

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 42 of 8315.3 SPI Interface PinsThe SPI interface uses the P1.3–P1.6 pins. These pins are configur

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 43 of 8316. Timer RegistersAll timer functions of the enCoRe II are provided by a single timer bl

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 44 of 83Table 16-3. Timer Capture 0 Rising (TIO0R) [0x22] [R/W]Bit # 7 6 5 4 3 2 1 0Field Capture

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 45 of 83Table 16-8. Programmable Interval Timer High (PITMRH) [0x27] [R]Bit # 7 6 5 4 3 2 1 0Fiel

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 46 of 8316.1.2 Timer CaptureCypress enCoRe II has two 8-bit captures. Each capture has separate r

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 47 of 83Table 16-12. Capture Interrupt Enable (TCAPINTE) [0x2B] [R/W]Bit # 7 6 5 4 3 2 1 0Field R

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 48 of 83Figure 16-3. Timer Functional Sequence Diagram[+] Feedback [+] Feedback

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 49 of 83Figure 16-4. 16-Bit Free Running Counter Loading Timing Diagramclk_syswritevalidaddrwrite

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 5 of 83Figure 5-2. CY7C63823 Die FormDie step = 1792 .98 μm x 2272.998 μm Die size = 1727 μm x 2

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 50 of 8317. Interrupt ControllerThe interrupt controller and its associated registers allow theus

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 51 of 8317.2 Interrupt ProcessingThe sequence of events that occur during interrupt processingfol

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 52 of 8317.5 Interrupt RegistersThe Interrupt Clear Registers (INT_CLRx) are used to enable the i

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 53 of 83 Table 17-5. Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W]Bit # 7 6 5 4 3 2 1 0Field ENSWINT

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 54 of 83Table 17-7. Interrupt Mask 1 (INT_MSK1) [0xE1] [R/W]Bit # 7 6 5 4 3 2 1 0Field TCAP0Int E

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 55 of 83Table 17-8. Interrupt Mask 0 (INT_MSK0) [0xE0] [R/W]Bit # 7 6 5 4 3 2 1 0Field GPIO Port

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 56 of 8318. Regulator Output18.1 VREG Control Table 18-1. VREG Control Register (VREGCR) [0x73

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 57 of 8319. USB/PS2 TransceiverAlthough the USB transceiver has features to assist in interfacing

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 58 of 8321. USB Device21.1 USB Device Address 21.2 Endpoint 0, 1, and 2 CountTable 21-1. USB D

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 59 of 8321.3 Endpoint 0 ModeBecause both firmware and the SIE are allowed to write to the Endpoin

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 6 of 83 Table 5-2. Pin Description32QFN 24QSOP 24SOIC18SIOC18PDIP16SOIC16PDIPName Description21 1

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 60 of 8321.4 Endpoint 1 and 2 ModeTable 21-4. Endpoint 1 and 2 Mode (EP1MODE – EP2MODE) [0x45, 0

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 61 of 83The three data buffers are used to hold data for both IN and OUT transactions. Each data b

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 62 of 8322.3 SETUP, IN, and OUT ColumnsDepending on the mode specified in the 'Encoding&apos

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 63 of 830010 OUT <=10, <>2 valid x STALL 0011 Yes Bad Status0010 OUT 2 valid 0 STALL 0011

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 64 of 831101 IN x x x STALL Stall INNAK IN1100 OUT x x x Ignore1100 IN x x x NAK If Enabled NAK

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 65 of 832A TMRCR First Edge Hold8-bit capture Prescale Cap0 16bit EnableReserved bbbbb--- 00000000

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 66 of 83Legend In the R/W column, b = Both Read and Writer = Read Onlyw = Write Onlyc = Read/Clear

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 67 of 8325. Voltage Vs CPU Frequency CharacteristicsFigure 25-1. Voltage vs CPU Frequency Charac

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 68 of 8326. Absolute Maximum RatingsExceeding maximum ratings may shorten the useful life of thed

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 69 of 83VDIDifferential Input Sensitivity 0.2 VVCMDifferential Input Common Mode Range0.8 2.5 VVSE

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 7 of 836. CPU ArchitectureThis family of microcontrollers is based on a high performance,8-bit, H

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 70 of 83USB DriverTR1Transition Rise Time CLOAD = 200 pF 75 nsTR2Transition Rise Time CLOAD = 600

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 71 of 83 1Figure 28-2. GPIO Timing DiagramFigure 28-1. Clock TimingFigure 28-3. USB Data Signal

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 72 of 83 Figure 28-5. Differential to EOP Transition Skew and EOP Width TPERIOD Differential Dat

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 73 of 83 Figure 28-7. SPI Master Timing, CPHA = 1MSBTMSULSBTMHDTSCKHTMDOSSSCK (CPOL=0)SCK (CPO

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 74 of 83Figure 28-9. SPI Master Timing, CPHA = 0Figure 28-10. SPI Slave Timing, CPHA = 0MSBTMSUL

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 75 of 8329. Ordering InformationOrdering Code FLASH Size RAM Size Package TypeCY7C63310-PXC 3K 12

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 76 of 8331. Package DiagramsFigure 31-1. 16-Pin (300-Mil) Molded DIP P1Figure 31-2. 16-Pin (150

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 77 of 83Figure 31-3. 18-Pin (300-Mil) Molded DIP P3Figure 31-4. 18-Pin (300-Mil) Molded SOIC S3D

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 78 of 83Figure 31-5. 24-Pin (300-Mil) SOIC S13Figure 31-6. 24-Pin QSOP O241SDIMENSIONS IN INCHES

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 79 of 83Figure 31-7. 32-Pin QFN PackageFigure 31-8. 32-Pin Sawn QFN Package51-85188-*B001-30999

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 8 of 837. CPU RegistersThe CPU registers in enCoRe II devices are in two banks with 256 registers

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 80 of 8332. Document History PageDocument Title: CY7C63310, CY7C638xx enCoRe™ II Low Speed USB Pe

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 81 of 83*G 424790 TYJ See ECN Minor text changes to make document more readableRemoved CY7C639xxRe

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 82 of 83*J 2147747 VGT/AESA 05/20/2008 TID number entered on page 1. Also changed the sentence “Hi

Document 38-08035 Rev. *K Revised December 08 2008 Page 83 of 83PSoC® is a registered trademark of Cypress MicroSystems. enCoRe is a trademark of Cypr

CY7C63310, CY7C638xxDocument 38-08035 Rev. *K Page 9 of 837.2 Addressing Modes7.2.1 Source ImmediateThe result of an instruction using this address