Cypress EZ-OTG CY7C67200 Specifications

CY7C67200EZ-OTG™ Programmable USBOn-The-Go Host/Peripheral ControllerCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709

CY7C67200Document Number: 38-08014 Rev. *J Page 10 of 93Power Savings and Reset DescriptionThe EZ-OTG modes and reset conditions are described in th

CY7C67200Document Number: 38-08014 Rev. *J Page 11 of 93the BIOS ROM, refer to the Programmers documentation and the BIOS documentation.During devel

CY7C67200Document Number: 38-08014 Rev. *J Page 12 of 93CPU Flags Register [0xC000] [R]Figure 7. CPU Flags Register Register Description The CPU Fl

CY7C67200Document Number: 38-08014 Rev. *J Page 13 of 93Bank Register [0xC002] [R/W]Figure 8. Bank Register Register Description The Bank register

CY7C67200Document Number: 38-08014 Rev. *J Page 14 of 93CPU Speed Register [0xC008] [R/W]Figure 10. CPU Speed Register Register DescriptionThe CPU

CY7C67200Document Number: 38-08014 Rev. *J Page 15 of 93Power Control Register [0xC00A] [R/W]Figure 11. Power Control Register Register Description

CY7C67200Document Number: 38-08014 Rev. *J Page 16 of 93Setting this bit to ‘1’ immediately initiates HALT mode. While in HALT mode, only the CPU is

CY7C67200Document Number: 38-08014 Rev. *J Page 17 of 93UART Interrupt Enable (Bit 3)The UART Interrupt Enable bit enables or disables the following

CY7C67200Document Number: 38-08014 Rev. *J Page 18 of 93USB Diagnostic Register [0xC03C] [R/W]Figure 14. USB Diagnostic Register Register Descripti

CY7C67200Document Number: 38-08014 Rev. *J Page 19 of 93Watchdog Timer Register [0xC00C] [R/W]Figure 15. Watchdog Timer Register Register Descripti

CY7C67200Document Number: 38-08014 Rev. *J Page 2 of 93ContentsIntroduction ...3

CY7C67200Document Number: 38-08014 Rev. *J Page 20 of 93Timer n Register [R/W] Timer 0 Register 0xC010 Timer 1 Register 0xC012Figure 16. Timer n

CY7C67200Document Number: 38-08014 Rev. *J Page 21 of 93Register Description The USB n Control register is used in both host and device mode. It mon

CY7C67200Document Number: 38-08014 Rev. *J Page 22 of 93USB Host Only RegistersThere are twelve sets of dedicated registers to USB host only operati

CY7C67200Document Number: 38-08014 Rev. *J Page 23 of 93Register DescriptionThe Host n Control register allows high-level USB transaction control.Pr

CY7C67200Document Number: 38-08014 Rev. *J Page 24 of 93Host n Count Register [R/W] Host 1 Count Register 0xC084 Host 2 Count Register 0xC0A4Figur

CY7C67200Document Number: 38-08014 Rev. *J Page 25 of 93Stall Flag (Bit 7)The Stall Flag bit indicates that the peripheral device replied with a Sta

CY7C67200Document Number: 38-08014 Rev. *J Page 26 of 93Register DescriptionThe Host n PID register is a write-only register that provides the PID a

CY7C67200Document Number: 38-08014 Rev. *J Page 27 of 93Host n Device Address Register [W] Host 1 Device Address Register 0xC088 Host 2 Device Add

CY7C67200Document Number: 38-08014 Rev. *J Page 28 of 931: Enable SOF/EOP timer interrupt0: Disable SOF/EOP timer interruptPort A Wake Interrupt Ena

CY7C67200Document Number: 38-08014 Rev. *J Page 29 of 93Port A Wake Interrupt Flag (Bit 6)The Port A Wake Interrupt Flag bit indicates remote wakeup

CY7C67200Document Number: 38-08014 Rev. *J Page 3 of 93IntroductionEZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first USB On-The-Go (OTG) host/per

CY7C67200Document Number: 38-08014 Rev. *J Page 30 of 93Host n SOF/EOP Counter Register [R] Host 1 SOF/EOP Counter Register 0xC094 Host 2 SOF/EOP

CY7C67200Document Number: 38-08014 Rev. *J Page 31 of 93Device n Endpoint n Control Register [R/W] Device n Endpoint 0 Control Register [Device 1:

CY7C67200Document Number: 38-08014 Rev. *J Page 32 of 930: Do not send StallISO Enable (Bit 4)The ISO Enable bit enables and disables an Isochronous

CY7C67200Document Number: 38-08014 Rev. *J Page 33 of 93Register DescriptionThe Device n Endpoint n Address register is used as the base pointer int

CY7C67200Document Number: 38-08014 Rev. *J Page 34 of 93Register DescriptionThe Device n Endpoint n Count register designates the maximum packet siz

CY7C67200Document Number: 38-08014 Rev. *J Page 35 of 93IN Exception Flag (Bit 8)The IN Exception Flag bit indicates when the device received an IN

CY7C67200Document Number: 38-08014 Rev. *J Page 36 of 93Device n Endpoint n Count Result Register [R/W] Device n Endpoint 0 Count Result Register [

CY7C67200Document Number: 38-08014 Rev. *J Page 37 of 93Device n Interrupt Enable Register [R/W] Device 1 Interrupt Enable Register 0xC08C Device

CY7C67200Document Number: 38-08014 Rev. *J Page 38 of 93EP5 Interrupt Enable (Bit 5)The EP5 Interrupt Enable bit enables or disables an endpoint fiv

CY7C67200Document Number: 38-08014 Rev. *J Page 39 of 93Device n Address Register [W] Device 1 Address Register 0xC08E Device 2 Address Register 0

CY7C67200Document Number: 38-08014 Rev. *J Page 4 of 93USB InterfaceEZ-OTG has two built-in Host/Peripheral SIEs that each have a single USB transce

CY7C67200Document Number: 38-08014 Rev. *J Page 40 of 930: Interrupt did not triggerReset Interrupt Flag (Bit 8)The Reset Interrupt Flag bit indicat

CY7C67200Document Number: 38-08014 Rev. *J Page 41 of 93Device n Frame Number Register [R] Device 1 Frame Number Register 0xC092 Device 2 Frame Nu

CY7C67200Document Number: 38-08014 Rev. *J Page 42 of 93Register DescriptionThe Device n SOF/EOP Count register must be written with the time expect

CY7C67200Document Number: 38-08014 Rev. *J Page 43 of 93D+ Pull-down Enable (Bit 7)The D+ Pull-down Enable bit enables or disables a pull-down resis

CY7C67200Document Number: 38-08014 Rev. *J Page 44 of 93Register DescriptionThe GPIO Control register configures the GPIO pins for various interface

CY7C67200Document Number: 38-08014 Rev. *J Page 45 of 93Register DescriptionThe GPIO 0 Output Data register controls the output data of the GPIO pin

CY7C67200Document Number: 38-08014 Rev. *J Page 46 of 93Register DescriptionThe GPIO 0 Input Data register reads the input data of the GPIO pins. Th

CY7C67200Document Number: 38-08014 Rev. *J Page 47 of 93Register DescriptionThe GPIO 0 Direction register controls the direction of the GPIO data pi

CY7C67200Document Number: 38-08014 Rev. *J Page 48 of 93HSS Control Register [0xC070] [R/W]Figure 48. HSS Control Register Register DescriptionThe

CY7C67200Document Number: 38-08014 Rev. *J Page 49 of 93Transmit Ready (Bit 4)The Transmit Ready bit is a read only bit that indicates if the HSS Tr

CY7C67200Document Number: 38-08014 Rev. *J Page 5 of 93UART Features Supports baud rates of 900 to 115.2K 8-N-1UART PinsI2C EEPROM Interface [2]EZ

CY7C67200Document Number: 38-08014 Rev. *J Page 50 of 93Register DescriptionThe HSS Baud Rate register sets the HSS Baud Rate. At reset, the default

CY7C67200Document Number: 38-08014 Rev. *J Page 51 of 93Register DescriptionThe HSS Data register contains data received on the HSS port (not for bl

CY7C67200Document Number: 38-08014 Rev. *J Page 52 of 93Register DescriptionThe HSS Receive Counter register designates the block byte length for th

CY7C67200Document Number: 38-08014 Rev. *J Page 53 of 93Register DescriptionThe HSS Transmit Counter register designates the block byte length for t

CY7C67200Document Number: 38-08014 Rev. *J Page 54 of 93Register DescriptionThe Interrupt Routing register allows the HPI port to take over some or

CY7C67200Document Number: 38-08014 Rev. *J Page 55 of 93HPI Swap 0 Enable (Bit 0)Both HPI Swap bits (bits 8 and 0) must be set to identical values.

CY7C67200Document Number: 38-08014 Rev. *J Page 56 of 93HPI Status Port [] [HPI: R] Figure 60. HPI Status Port Register DescriptionThe HPI Status P

CY7C67200Document Number: 38-08014 Rev. *J Page 57 of 93Done2 Flag (Bit 3)In host mode the Done2 Flag bit is a read-only bit that indicates if a hos

CY7C67200Document Number: 38-08014 Rev. *J Page 58 of 93Register DescriptionThe SPI Configuration register controls the SPI port. Fields apply to bo

CY7C67200Document Number: 38-08014 Rev. *J Page 59 of 93SPI Control Register [0xC0CA] [R/W] Figure 62. SPI Control Register Register DescriptionThe

CY7C67200Document Number: 38-08014 Rev. *J Page 6 of 93HSS PinsHost Port Interface (HPI)EZ-OTG has an HPI interface. The HPI interface provides DMA

CY7C67200Document Number: 38-08014 Rev. *J Page 60 of 93Receive Bit Length (Bits [2:0])The Receive Bit Length field controls whether a full byte or

CY7C67200Document Number: 38-08014 Rev. *J Page 61 of 93Register DescriptionThe SPI Status register is a read only register that provides status for

CY7C67200Document Number: 38-08014 Rev. *J Page 62 of 93Register DescriptionThe SPI CRC Control register provides control over the CRC source and po

CY7C67200Document Number: 38-08014 Rev. *J Page 63 of 93SPI Data Register [0xC0D6] [R/W]Figure 68. SPI Data Register Register DescriptionThe SPI Da

CY7C67200Document Number: 38-08014 Rev. *J Page 64 of 93SPI Transmit Count Register [0xC0DA] [R/W] Figure 70. SPI Transmit Count Register Register

CY7C67200Document Number: 38-08014 Rev. *J Page 65 of 93Register DescriptionThe SPI Receive Count register designates the block byte length for the

CY7C67200Document Number: 38-08014 Rev. *J Page 66 of 93ReservedAll reserved bits must be written as ‘0’.UART Status Register [0xC0E2] [R]Figure 74.

CY7C67200Document Number: 38-08014 Rev. *J Page 67 of 93Pin DiagramThe following describes the CY7C67200 48-pin FBGA.Figure 76. EZ-OTG Pin DiagramP

CY7C67200Document Number: 38-08014 Rev. *J Page 68 of 93H5 GPIO22/nWR IO GPIO22: General Purpose IOnWR: HPI nWRG5 GPIO21/nCS IO GPIO21: General Purp

CY7C67200Document Number: 38-08014 Rev. *J Page 69 of 93Absolute Maximum RatingsThis section lists the absolute maximum ratings. Stresses above thos

CY7C67200Document Number: 38-08014 Rev. *J Page 7 of 93Component details: D1 and D2: Schottky diodes with a current rating greater than 60 mA. C1:

CY7C67200Document Number: 38-08014 Rev. *J Page 70 of 93DC Characteristics Notes13. All tests were conducted with Charge pump off.14. ICC and ICCB

CY7C67200Document Number: 38-08014 Rev. *J Page 71 of 93USB TransceiverUSB 2.0-compatible in full- and low-speed modes. This product was tested as c

CY7C67200Document Number: 38-08014 Rev. *J Page 72 of 93Clock Timing I2C EEPROM Timing Parameter Description Min. Typ. Max. UnitfCLKClock Frequenc

CY7C67200Document Number: 38-08014 Rev. *J Page 73 of 93Figure 77. HPI (Host Port Interface) Write Cycle Timing Parameter Description Min. Typical

CY7C67200Document Number: 38-08014 Rev. *J Page 74 of 93HPI (Host Port Interface) Read Cycle Timing Parameter Description Min. Typ. Max. UnittASUAdd

CY7C67200Document Number: 38-08014 Rev. *J Page 75 of 93HSS BYTE Mode Transmit qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in th

CY7C67200Document Number: 38-08014 Rev. *J Page 76 of 93Hardware CTS/RTS HandshaketCTSset-up: HSS_CTS setup time before HSS_RTS = 1.5T min.tCTShol

CY7C67200Document Number: 38-08014 Rev. *J Page 77 of 93Register SummaryTable 42. Register Summary R/W Address Register Bit 15 Bit 14 Bit 13 Bit 1

CY7C67200Document Number: 38-08014 Rev. *J Page 78 of 93R/W 0xC024 GPIO 1 Output Data GPIO31 GPIO30 GPIO29 Reserved GPIO24 0000 0000GPIO23 GPIO22 GP

CY7C67200Document Number: 38-08014 Rev. *J Page 79 of 93R/W 0xC090 Host 1 Status VBUS InterruptFlagIDInterruptFlagReserved SOF/EOPInterruptFlagReser

CY7C67200Document Number: 38-08014 Rev. *J Page 8 of 93Crystal InterfaceThe recommended crystal circuit to be used with EZ-OTG is shown in Figure 4.

CY7C67200Document Number: 38-08014 Rev. *J Page 80 of 93R/W 0xC0D6 SPI Data Port t Reserved xxxx xxxxData xxxx xxxxR/W 0xC0D8 SPI Transmit Address A

CY7C67200Document Number: 38-08014 Rev. *J Page 81 of 93Ordering InformationOrdering Code DefinitionsTable 43. Ordering InformationOrdering Code Pa

CY7C67200Document Number: 38-08014 Rev. *J Page 82 of 93Package DiagramFigure 78. 48-ball (7.00 mm × 7.00 mm × 1.2 mm) FBGA BA4851-85096 *I

CY7C67200Document Number: 38-08014 Rev. *J Page 83 of 93Acronyms Document ConventionsUnits of Measure Table 44. Acronyms Used in this DocumentAcron

CY7C67200Document Number: 38-08014 Rev. *J Page 84 of 93ErrataThis section describes the errata for the CY7C67200. Details include errata trigger co

CY7C67200Document Number: 38-08014 Rev. *J Page 85 of 931. HPI Write to SIE Registers Problem DefinitionWriting to the SIE2 Control register via HP

CY7C67200Document Number: 38-08014 Rev. *J Page 86 of 933. UART Does Not Recognize Framing Errors Problem DefinitionThe UART is not designed to rec

CY7C67200Document Number: 38-08014 Rev. *J Page 87 of 935. VBUS Interrupt (VBUS Valid) Requires Debouncing Problem DefinitionThe VBUS interrupt in

CY7C67200Document Number: 38-08014 Rev. *J Page 88 of 937. Un-Initialized SIExmsg Registers Problem DefinitionThe SIE1msg and SIE2msg Registers [0x

CY7C67200Document Number: 38-08014 Rev. *J Page 89 of 939. Peripheral Short Packet Issue Problem DefinitionWhen a SIE is configured as a peripheral

CY7C67200Document Number: 38-08014 Rev. *J Page 9 of 93Operational ModesThere are two modes of operation: Coprocessor and Stand-alone.Coprocessor Mo

CY7C67200Document Number: 38-08014 Rev. *J Page 90 of 93 Problem DefinitionWhen a SIE is configured as a peripheral, data toggle corruption as spec

CY7C67200Document Number: 38-08014 Rev. *J Page 91 of 93Document History PageDocument Title: CY7C67200 EZ-OTG™ Programmable USB On-The-Go Host/Perip

CY7C67200Document Number: 38-08014 Rev. *J Page 92 of 93*J 4082823 PRJI 07/31/2013 Added Errata footnotes (Note 1, 2, 7, 8, 9, 10, 11).Updated Inter

Document Number: 38-08014 Rev. *J Revised July 31, 2013 Page 93 of 93All products and company names mentioned in this document may be the trademarks