Cypress EZ-USB Series 2100 User's Guide Page 227
- Page / 239
- Table of contents
- TROUBLESHOOTING
- BOOKMARKS
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Bulk Transfers with the EZ-USB SX2™ Connected
to an Intel
XScale™ DMA Interface
3
Connection Diagram
Figure 1 shows the complete set of signal connections
between the SX2 and the XScale device. The SX2 READY
signal can be connected to the XScale RDY signal. This will
allow throttling of consecutive command writes without
firmware having to detect the READY signal returning high.
An alternative method would be to connect the SX2 READY
signal to an XScale GPIO pin (programmed to trigger an
interrupt on the rising edge). The INT signal should be
connected to a GPIO pin (programmed to trigger an interrupt
on the falling edge) on the XScale to ensure timely reading of
either the interrupt status or the requested register data value.
The SX2 FIFOADR[2:0] pins are connected to address lines
MA[N], MA[N-1], MA[N-2] for DMA memory addressing for
sourcing or sinking the SX2 endpoint data. The SX2 chip
select (CS# function of Flag D) can also be used to localize
addressing of the SX2 on a common address bus.
In this scheme the SX2 slave output enable (SLOE) and slave
read (SLRD) signals are tied together and driven by the single
XScale read (nOE) signal which the XScale DMA drives
during read burst operations.
SX2 write operations require a single slave write (SLWR)
signal and are driven by the single XScale Write (nPWE)
signal, which the XScale DMA drives during write burst opera-
tions.
Data is read from or written to the SX2 in either 8-bit or 16-bit
operations. When programmed for 8-bit data operations, then
of the 16 total data lines, only the FD [7:0] pins are required
for all command, status, and data operations. When
programmed for 16-bit operations (as this example shows),
the second byte in a 16-bit data word is carried on the upper
data pins (FD [15:8]). The first byte corresponds to the least
significant byte (LSB) of a word and the second byte corre-
sponds to the most significant byte (MSB) of a word.
command and status operations are always 8-bit.
The SX2 Flag B is connected to the XScale DMA Request
(DREQ0) signal for the DMA channel. The currently
programmed SX2 endpoint FIFO Flag B is used for throttling
the DMA request flow.
Figure 1. SX2 to XScale Interconnect Diagram
CYPRESS SX2
(CY7C68001)
IFCLK
INT
READY
FLAG B
CS#
SLOE
SLRD
SLWR
PKTEND
FD[ 7:0]
FD[15:8]
FIFOADR[0]
FIFOADR[1]
FIFOADR[2]
Intel XScale
PXA255
I/O
MEMCLK
GPIOx (INT)
RDY
DREQ0
nCS1
nOE
nPWE
MD[ 7:0]
MD[15:8]
MA[N-2]
MA[N-1]
MA[N]
16-Bit Data Byte1 / 8-Bit Data /
Command/Status Bytes
OUT Endpoint2 Empty /
IN Endpoint6 Full
Read/Interrupt Status Ready
Command/Status Select
Command Select Ready
SX2 Chip Select
Read Output Enable
Read Access
Write Access
Pull Up
16-Bit Data Byte2
FIFO 2468 Select1
FIFO 2468 Select2
USB D+/D-
USB VBUS
USBD+
USBD-
- AYO DE 2007 1
- PROYECTO FINAL DE CARRERA: 3
- Índice general 5
- 4 ÍNDICE GENERAL 6
- II Anexos 75 7
- 6 ÍNDICE GENERAL 8
- Capítulo 1 11
- Objetivo y alcance 11
- 1.2. Objetivos y alcances 12
- 1.3. Posibles ampliaciones 12
- 1.3. POSIBLES AMPLIACIONES 11 13
- Capítulo 2 15
- Estructura de la Memoria 15
- Capítulo 3 17
- 3.2. Definici ones previas 18
- Facilidad de uso 19
- 3.4. Componentes del bus 22
- 3.5. División de tar eas 22
- 3.8. Transferencias bulk 25
- Capítulo 4 27
- Descripción del kit 27
- Esquemas PCB 29
- Capítulo 5 31
- 5.2. REQUISITOS PREVIOS 31 33
- SIEMaster. Modo 1 B 37
- Capítulo 6 55
- 6.7. Conclus iones 72
- Capítulo 7 73
- Contenido del CD-ROM 73
- 7.2. Notas de aplicación 74
- Parte II 77
- Capítulo 8 79
- Manuales de referencia 79
- EZ-USB SX2 81
- Getting Started 81
- Development Kit Manual 81
- Page 2 Rev 2.0 86
- Page 4 Rev 2.0 88
- Page 6 Rev 2.0 90
- Page 8 Rev 2.0 92
- Page 10 Rev 2.0 94
- Page 12 Rev 2.0 96
- EP2 FIFO 97
- EP6 FIFO 97
- EP8 FIFO 97
- EP4 FIFO 97
- Page 14 Rev 2.0 98
- Page 16 Rev 2.0 100
- Flag.hex 101
- Page 18 Rev 2.0 102
- “Small” 16x8 000 24LC00 103
- 128x8 000 24LC01 103
- 256x8 000 24LC02 103
- “Large” 8Kx8 001 24LC64/5 103
- Page 20 Rev 2.0 104
- Table 5. P8 Pinout 105
- P8 Pinout 105
- Table 6. Pin 9 Pinout 106
- P9 Pinout 106
- Page 24 Rev 2.0 108
- 3901 North First Street 109
- San Jose, CA 95134-1599 109
- Cypress Disclaimer Agreement 110
- Table of Contents 111
- 1.0 Purpose 113
- 2.0 Hardware Setup 114
- 3.0 Using SIEMaster 115
- SX2 SIEMaster User’s Guide 116
- 3.2 Custom Enumeration 118
- 3.3 Monitor Interrupts 118
- 3.4 Read Register 118
- 3.5 Write Register 119
- 3.6 Read Setup 121
- 4.0 Summary 124
- CY7C6800 127
- CY3682 Design Notes 169
- August 16, 2005 181
- Part Numbers Affected 181
- EZ-USB SX2 Errata Summary 181
- References 182
- Document History Page 183
- Troubleshooting 192
- Capítulo 9 193
- Notas de aplicación 193
- Introduction 195
- Writing/Reading Registers 195
- FIFO Access 196
- Approved AN4050 7/13/04 kkv 197
- EZ-USB FX2™/AT2™/SX2™ 199
- Approved AN065 10/14/03 kkv 201
- Background 203
- Considerations with USB 2.0 203
- Solution 203
- Conclusion 203
- USB Signals 206
- Power and Ground 207
- Crystal or Oscillator 208
- Connection Scheme 209
- Important Considerations 211
- Connection Diagram 212
- Writing Commands to the SX2 213
- Reading Status from the SX2 214
- XScale™ DMA Interface 225
- CYPRESS SX2 227
- (CY7C68001) 227
- Intel XScale 227
- Bibliografía 239
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