Cypress CY7C1318CV18-167BZC User Manual download pdf

PRELIMINARY

18-Mbit DDR-II SRAM 2-Word

Burst Architecture

CY7C1316CV18

CY7C1916CV18

CY7C1318CV18

CY7C1320CV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-07160 Rev. *B Revised September 20, 2006

Features

• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

• 300-MHz clock for high bandwidth

• 2-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) @ 300 MHz

• Two input clocks (K and K

) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C

) to minimize

clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ

) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• DDR-II operates with 1.5 cycle read latency when the

DLL is enabled

• Operates like a DDR-I device with 1 cycle read latency

in DLL off mode

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V

)

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Offered in both lead-free and non lead-free packages

• JTAG 1149.1-compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1316CV18 – 2M x 8

CY7C1916CV18 – 2M x 9

CY7C1318CV18 – 1M x 18

CY7C1320CV18 – 512K x 36

Functional Description

The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18 and

CY7C1320CV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry

and a 1-bit burst counter. Addresses for Read and Write are

latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K

. Read

data is driven on the rising edges of C and C

if provided, or on

the rising edge of K and K

if C/C are not provided. Each

address location is associated with two 8-bit words in the case

of CY7C1316CV18 and two 9-bit words in the case of

CY7C1916CV18 that burst sequentially into or out of the

device. The burst counter always starts with a “0” internally in

the case of CY7C1316CV18 and CY7C1916CV18. On

CY7C1318CV18 and CY7C1320CV18, the burst counter

takes in the least significant bit of the external address and

bursts two 18-bit words in the case of CY7C1318CV18 and

two 36-bit words in the case of CY7C1320CV18 sequentially

into or out of the device.

Asynchronous inputs include output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the

two output echo clocks CQ/CQ

, eliminating the need for

separately capturing data from each individual DDR SRAM in

the system design. Output data clocks (C/C) enable maximum

system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled

by the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz

Maximum Operating Current 600 580 550 500 450 mA

1 2 3 4 5 6 ... 27 28

Summary of Contents

Page 1 - Burst Architecture

PRELIMINARY18-Mbit DDR-II SRAM 2-WordBurst ArchitectureCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Cypress Semiconductor Corporation • 198 Champi

Page 2

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 10 of 28 Write Cycle Descriptions (CY7C1316CV18

Page 3

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 11 of 28Write Cycle Descriptions (CY7C1320CV18) [

Page 4

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 12 of 28IEEE 1149.1 Serial Boundary Scan (JTAG)Th

Page 5

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 13 of 28is loaded into the instruction register u

Page 6

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 14 of 28TAP Controller State Diagram[9]Note: 9. T

Page 7

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 15 of 28 TAP Controller Block DiagramTAP Electri

Page 8

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 16 of 28Set-up TimestTMSSTMS Set-up to TCK Clock

Page 9

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 17 of 28 Identification Register DefinitionsIn

Page 10 - CY7C1320CV18

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 18 of 28Boundary Scan Order Bit # Bump ID Bit # B

Page 11

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 19 of 28Power-up Sequence in DDR-II SRAM[15]DDR-I

Page 12

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 2 of 28 Logic Block Diagram (CY7C1316CV18)CLKA(19

Page 13

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 20 of 28Maximum Ratings(Above which the useful li

Page 14

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 21 of 28Note: 21. Unless otherwise noted, test co

Page 15

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 22 of 28Switching Characteristics Over the Operat

Page 16

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 23 of 28tCQOHtCHCQXEcho Clock Hold after C/C Cloc

Page 17

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 24 of 28Switching Waveforms[28, 29, 30]Notes: 28.

Page 18

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 25 of 28Ordering Information “Not all of the spee

Page 19

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 26 of 28250 CY7C1316CV18-250BZI 51-85180 165-ball

Page 20

PRELIMINARY CY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 27 of 28© Cypress Semiconductor Corporation, 2006

Page 21

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 28 of 28Document History PageDocument Title: CY7C

Page 22

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 3 of 281M x 18 ArrayWriteRegWriteRegLogic Block D

Page 23

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 4 of 28 Pin Configurations CY7C1316CV18 (2M x 8)2

Page 24

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 5 of 28Pin Configurations (continued)CY7C1318CV1

Page 25

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 6 of 28 Pin Definitions Pin Name I/O Pin Descript

Page 26

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 7 of 28Functional OverviewThe CY7C1316CV18, CY7C1

Page 27 - PRELIMINARY

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 8 of 28edge of the output clock (C or C, or K and

Page 28

PRELIMINARYCY7C1316CV18CY7C1916CV18CY7C1318CV18CY7C1320CV18Document Number: 001-07160 Rev. *B Page 9 of 28 Notes: 1. The above application shows tw

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Cypress CY7C1318CV18-167BZC User Manual

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