Cypress NoBL CY7C1462AV25 User Manual Page 1

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ ArchitectureCY7C1460AV25CY7C1462AV25CY7C1464AV25Cypress Semiconductor Corporation • 19

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 10 of 27IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1460AV25/CY7C1462AV25/CY

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 11 of 27When the TAP controller is in the Capture-IR state, the twoleast signif

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 12 of 27When this scan cell, called the “extest output bus tri-state,” islatche

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 13 of 272.5V TAP AC Test ConditionsInput pulse levels ...

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 14 of 27Scan Register SizesRegister Name Bit Size (x36) Bit Size (x18) Bit Size

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 15 of 27165-ball FBGA Boundary Scan Order[12]CY7C1460AV25 (1M x 36), CY7C1462AV

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 16 of 27209-ball FBGA Boundary Scan Order[12, 13]CY7C1464AV25 (512K x 72)Bit# B

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 17 of 27Maximum Ratings (Above which the useful life may be impaired. For user

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 18 of 27Capacitance[16]Parameter Description Test Conditions100 TQFP Max.165 FB

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 19 of 27Switching Characteristics Over the Operating Range[21, 22]Parameter Des

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 2 of 27 Selection Guide250 MHz 200 MHz 167 MHz UnitMaximum Access Time 2.6 3.2

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 20 of 27Switching WaveformsRead/Write/Timing[23, 24, 25]NOP, STALL and DESELECT

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 21 of 27ZZ Mode Timing[27, 28]Notes: 27. Device must be deselected when enterin

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 22 of 27Ordering InformationNot all of the speed, package and temperature range

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 23 of 27250 CY7C1460AV25-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 24 of 27Package DiagramsNOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DO

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 25 of 27Package Diagrams (continued)A1PIN 1 CORNER17.00±0.1015.00±0.107.001.00Ø

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 26 of 27© Cypress Semiconductor Corporation, 2006. The information contained he

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 27 of 27Document History PageDocument Title: CY7C1460AV25/CY7C1462AV25/CY7C1464

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 3 of 27Pin ConfigurationsAAAAA1A0VSSVDDAAAAAAVDDQVSSDQb DQb DQb VSSVDDQDQb DQb

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 4 of 27Pin Configurations (continued)234 5671ABCDEFGHJKLMNPRTDONC/576MNC/1GDQPc

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 5 of 27Pin Configurations (continued)ABCDEFGHJKLMNPRTUVW123456789 1110DQgDQgDQg

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 6 of 27CE1Input-SynchronousChip Enable 1 Input, active LOW. Sampled on the risi

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 7 of 27Functional OverviewThe CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 aresynchro

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 8 of 27CY7C1460AV25, BWa,b,c,d for CY7C1460AV25 and BWa,b forCY7C1462AV25) inpu

CY7C1460AV25CY7C1462AV25CY7C1464AV25Document #: 38-05354 Rev. *D Page 9 of 27Partial Write Cycle Description[1, 2, 3, 8]Function (CY7C1460AV25) WE BW