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Cypress CY7C107BN User Manual

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1M x 1 Static RAM
CY7C107BN
CY7C1007BN
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06426 Rev. ** Revised February 1, 2006
Features
•High speed
—t
AA
= 15 ns
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Functional Description
The CY7C107BN and CY7C1007BN are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE
) and three-state drivers. These devices have an
automatic power-down feature that reduces power
consumption by more than 65% when deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. Data on the input pin
(D
IN
) is written into the memory location specified on the
address pins (A
0
through A
19
).
Reading from the devices is accomplished by taking Chip
Enable (CE
) LOW while Write Enable (WE) remains HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the data output
(D
OUT
) pin.
The output pin (D
OUT
) is placed in a high-impedance state
when the device is deselected (CE
HIGH) or during a write
operation (CE
and WE LOW).
The CY7C107BN is available in a standard 400-mil-wide SOJ;
the CY7C1007BN is available in a standard 300-mil-wide SOJ
Logic Block Diagram Pin Configuration
Top View
SOJ
512 x 2048
ARRA
Y
A
5
A
6
A
7
COLUMN
DECODER
ROW DECODER
SENSE AMPS
POWER
DOWN
WE
CE
INPUT BUFFER
D
OUT
D
IN
A
4
A
3
A
2
A
1
A
0
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
12
13
25
28
27
26
GND
A
11
A
12
A
13
A
14
WE
V
CC
A
9
A
10
CE
A
0
D
OUT
D
IN
A
8
A
7
A
6
A
2
A
1
A
4
NC
NC
A
15
A
16
A
8
A
12
A
14
A
16
A
15
A
10
A
11
A
13
A
17
A
18
A
19
A
17
A
18
A
19
A
5
A
3
A
9
Selection Guide
7C107BN-15
7C1007BN-15
Maximum Access Time (ns) 15
Maximum Operating Current (mA) 80
Maximum CMOS Standby Current I
SB2
(mA) 2
[+] Feedback
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Summary of Contents

Page 1 - 1M x 1 Static RAM

1M x 1 Static RAMCY7C107BNCY7C1007BNCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #: 001-06

Page 2 - CY7C1007BN

CY7C107BNCY7C1007BNDocument #: 001-06426 Rev. ** Page 2 of 7Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not t

Page 3

CY7C107BNCY7C1007BNDocument #: 001-06426 Rev. ** Page 3 of 7AC Test Loads and WaveformsSwitching Characteristics[5] Over the Operating Range7C107BN-

Page 4

CY7C107BNCY7C1007BNDocument #: 001-06426 Rev. ** Page 4 of 7Switching WaveformsRead Cycle No. 1[10, 11]Read Cycle No. 2[11, 12]Write Cycle No. 1 (CE

Page 5

CY7C107BNCY7C1007BNDocument #: 001-06426 Rev. ** Page 5 of 7Write Cycle No. 2 (WE Controlled)[13]Truth TableCE WE DOUTMode PowerH X High Z Power-Dow

Page 6

CY7C107BNCY7C1007BNDocument #: 001-06426 Rev. ** Page 6 of 7© Cypress Semiconductor Corporation, 2006. The information contained herein is subject

Page 7

CY7C107BNCY7C1007BNDocument #: 001-06426 Rev. ** Page 7 of 7Document History PageDocument Title: CY7C107BN/CY7C1007BN 1M x 1 Static RAMDocument Numb

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