Cypress DCT-1D manuals

Cypress DCT-1D User's Guide (82 pages)

Brand: Cypress | Category: Unknown | Size: 0.53 MB |

English

Table of contents

Laboratory manual for TSEA44

1

Contents

3

CONTENTS

4

The system

7

1.2 Hardware

8

1.2. HARDWARE

9

1.2.3 Virtex-II 4000 FPGA

10

1.3 Open RISC

11

CHAPTER 1. THE SYST EM

12

1.3.3 OR1200 CPU

13

1.3.5 Memory Controller

15

1.3.6 Ethernet Controller

15

1.4 Software

16

1.4. SOFTWARE

17

1.4.4 µClinux

20

Lab task 0 - Build a UART in

23

2.2.2 The hardware

24

2.2.3 A simple testbench

24

2.2. A SIMPLE UART

25

2.3 Exercises

26

Preparation task 1

26

Laboration task 1

26

2.4 gtkterm usage

27

Wishbone bus

29

Master Slave

30

3.2.1 A Wishbone Interconnect

31

3.3 A Simple Computer

32

Preparation task 2

33

Preparation task 3

34

Preparation task 4

34

Laboration task 2

35

3.4 A Benchmark Program

36

3.4. A BENCHMARK PROGRAM

37

Preparation task 5

38

Laboration task 3

39

3.6 Useful Commands

40

3.7.1 A Note on Volatile

41

Lab task 2 - Design a JPEG

43

Preparation task 6

44

4.2.2 Distributed RAMs

45

Preparation task 7

46

Laboration task 4

47

Laboration task 5

47

4.3 Introduction to µClinux

47

Laboration task 6

47

Laboration task 7

48

4.4 Introduction to jpegﬁles

48

Preparation task 8

49

Laboration task 8

50

Laboration task 9

50

4.5 Timestamps

50

4.6 Quantization

51

Preparation task 9

52

4.7 Tips and tricks

53

Lab task 3

55

WAITREADY

56

GETBLOCK

56

WAITREADY_LAST RELEASEBUS

56

5.1.2 jpeg_dma.sv

56

Preparation task 10

58

Laboration task 10

58

Laboration task 11

58

Laboration task 12

58

CHAPTER 5. LAB TASK 3

60

Chapter 6

61

Preparation task 11

62

Preparation task 12

62

6.2 Adding a New Instruction

62

6.3 Proposed Architecture

63

6.4 Hardware Implementation

64

6.5 Software Implementation

65

Laboration task 13

67

Laboration task 14

67

6.7 Tips and tricks

68

6.9 Beyond tsea44

70

Bibliography

71

BIBLIOGRAPHY

72

Open RISC Reference Platform

73

A.2 Interrupts

74

The Wishbone speciﬁcation

75

B.2 Interface signals

76

−WSS−CLK_I

77

B.5 System Verilog Interface

79

Tips & Trix

81

APPENDIX C. TIPS & TRIX

82

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