Cypress NoBL CY7C1355C User Manual

9-Mbit (256K x 36/512K x 18)Flow-Through SRAM with NoBL™ Architecture CY7C1355CCY7C1357CCypress Semiconductor Corporation • 198 Champion Court • San

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 10 of 28NOP/WRITE ABORT (Begin Burst) None L H L L L L H X L L->H Tri-StateWRITE ABORT (Contin

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 11 of 28IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1355C/CY7C1357C incorporates a serial boun

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 12 of 28Diagram. Upon power-up, the instruction register is loadedwith the IDCODE instruction. It

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 13 of 28TAP Timing TAP AC Switching Characteristics Over the Operating Range[10, 11]Parameter Des

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 14 of 283.3V TAP AC Test ConditionsInput pulse levels...

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 15 of 28Scan Register SizesRegister Name Bit Size (x36) Bit Size (x18)Instruction 3 3Bypass 1 1ID

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 16 of 28119-ball BGA Boundary Scan Order CY7C1355C (256K x 36) CY7C1357C (512K x 18)Bit# ball IDS

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 17 of 28165-ball FBGA Boundary Scan Order CY7C1355C (256K x 36) CY7C1357C (512K x 18)Bit# ball I

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 18 of 28Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not te

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 19 of 28Capacitance[15]Parameter Description Test Conditions100 TQFPMax.119 BGAMax.165 FBGAMax. U

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 2 of 2812CMODEBWABWBWECE1CE2CE3OEREAD LOGICDQsDQPADQPBDQPCDQPDMEMORYARRAYEINPUTREGISTERBWCBWDADDR

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 20 of 28Switching Characteristics Over the Operating Range[16, 17]Parameter Description–133 –100U

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 21 of 28Switching WaveformsRead/Write Waveforms[22, 23, 24]Notes: 22.For this waveform ZZ is tied

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 22 of 28NOP, STALL and DESELECT Cycles[22, 23, 25]Note: 25.The IGNORE CLOCK EDGE or STALL cycle (

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 23 of 28ZZ Mode Timing[26, 27]Notes: 26.Device must be deselected when entering ZZ mode. See trut

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 24 of 28Ordering InformationNot all of the speed, package and temperature ranges are available. P

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 25 of 28Package Diagrams NOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DOES NOT INCLUDE M

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 26 of 28Package Diagrams (continued)1.2720.322165437LEABDCHGFKJUPNMTR12.0019.5030° TYP.2.40 MAX.

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 27 of 28© Cypress Semiconductor Corporation, 2006. The information contained herein is subject t

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 28 of 28Document History PageDocument Title: CY7C1355C/CY7C1357C 9-Mbit (256K x 36/512K x 18) F

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 3 of 28Pin Configurations 100-Pin TQFP PinoutAAAAA1A0NC/288MNC/144MVSSVDDNC/36MAAAAAADQPBDQBDQBVD

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 4 of 28Pin Configurations (continued)100-Pin TQFP PinoutAAAAA1A0NC/288MNC/144MVSSVDDNC/36MAAAAAA

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 5 of 28Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNC/576MNC/1GDQPCDQCDQDDQCDQDAA

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 6 of 28Pin Configurations (continued)165-Ball FBGA Pinout (3 Chip enable with JTAG)CY7C1355C (25

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 7 of 28Pin Definitions Name I/O DescriptionA0, A1, A Input-SynchronousAddress Inputs used to sele

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 8 of 28Functional OverviewThe CY7C1355C/CY7C1357C is a synchronous flow-throughburst SRAM designe

CY7C1355CCY7C1357CDocument #: 38-05539 Rev. *E Page 9 of 28precaution, DQs and DQPX are automatically tri-stated duringthe data portion of a write cy