2-Mbit (128K x 16) Static RAMCY62136EV30MoBL®Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document
CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 10 of 12 Package DiagramsA1A1 CORNER0.750.75Ø0.30±0.05(48X)Ø0.25 M C A BØ0.05 M CBA0.15(4X)0.21±0.0
CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 11 of 12© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to
CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 12 of 12Document History PageDocument Title: CY62136EV30 MoBL® 2-Mbit (128K x 16) Static RAMDocumen
CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 2 of 12 Notes: 2. NC pins are not connected on the die.3. Pins D3, H1, G2, and H6 in the BGA packag
CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 3 of 12Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not teste
CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 4 of 12 Thermal Resistance[8]Parameter Description Test ConditionsVFBGAPackage TSOP IIPackage UnitΘ
CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 5 of 12 Switching Characteristics Over the Operating Range[10, 11, 12, 13]Parameter Description45 n
CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 6 of 12Switching Waveforms[14, 15]Read Cycle 1 (Address Transition Controlled)[14, 15]Read Cycle No
CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 7 of 12Write Cycle No. 1 (WE Controlled)[13, 17, 18]Write Cycle No. 2 (CE Controlled)[13, 17, 18]No
CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 8 of 12Write Cycle No. 3 (WE Controlled, OE LOW)[18]Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[
CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 9 of 12Truth TableCE WE OE BHE BLE Inputs/Outputs Mode PowerH X X X X High Z Deselect/Power-down St
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