Cypress Perform CY62136EV30 User Manual

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2-Mbit (128K x 16) Static RAM
CY62136EV30
MoBL
®
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-05569 Rev. *B Revised January 6, 2006
Features
Very high speed: 45 ns
Wide voltage range: 2.20V–3.60V
Pin-compatible with CY62136CV30
Ultra low standby power
Typical standby current: 1µA
Maximum standby current: 7µA
Ultra-low active power
Typical active current: 2 mA @ f = 1 MHz
Easy memory expansion with CE
, and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Offered in a Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Functional Description
[1]
The CY62136EV30 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE
HIGH). The input/output pins (I/O
0
through
I/O
15
) are placed in a high-impedance state when: deselected
(CE
HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE
, BLE HIGH),
or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE
) and Output Enable (OE) LOW while forcing the
Write Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
128K x 16
RAM Array
I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
CE
WE
BLE
BHE
A
16
A
0
A
1
A
9
A
10
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Summary of Contents

Page 1 - 2-Mbit (128K x 16) Static RAM

2-Mbit (128K x 16) Static RAMCY62136EV30MoBL®Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document

Page 2

CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 10 of 12 Package DiagramsA1A1 CORNER0.750.75Ø0.30±0.05(48X)Ø0.25 M C A BØ0.05 M CBA0.15(4X)0.21±0.0

Page 3

CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 11 of 12© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to

Page 4

CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 12 of 12Document History PageDocument Title: CY62136EV30 MoBL® 2-Mbit (128K x 16) Static RAMDocumen

Page 5

CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 2 of 12 Notes: 2. NC pins are not connected on the die.3. Pins D3, H1, G2, and H6 in the BGA packag

Page 6

CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 3 of 12Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not teste

Page 7

CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 4 of 12 Thermal Resistance[8]Parameter Description Test ConditionsVFBGAPackage TSOP IIPackage UnitΘ

Page 8

CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 5 of 12 Switching Characteristics Over the Operating Range[10, 11, 12, 13]Parameter Description45 n

Page 9

CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 6 of 12Switching Waveforms[14, 15]Read Cycle 1 (Address Transition Controlled)[14, 15]Read Cycle No

Page 10 - CY62136EV30

CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 7 of 12Write Cycle No. 1 (WE Controlled)[13, 17, 18]Write Cycle No. 2 (CE Controlled)[13, 17, 18]No

Page 11

CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 8 of 12Write Cycle No. 3 (WE Controlled, OE LOW)[18]Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[

Page 12

CY62136EV30MoBL®Document #: 38-05569 Rev. *B Page 9 of 12Truth TableCE WE OE BHE BLE Inputs/Outputs Mode PowerH X X X X High Z Deselect/Power-down St

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