Cypress CY7B991 User Manual download pdf

CY7B991

CY7B992

Programmable Skew Clock Buffer

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-07138 Rev. *B Revised June 22, 2007

Features

■ All output pair skew <100 ps typical (250 maximum)

■ 3.75 to 80 MHz output operation

■ User selectable output functions

❐ Selectable skew to 18 ns

❐ Inverted and non-inverted

❐ Operation at 1⁄2 and 1⁄4 input frequency

❐ Operation at 2x and 4x input frequency (input as low as 3.75

MHz)

■ Zero input to output delay

■ 50% duty cycle outputs

■ Outputs drive 50Ω terminated lines

■ Low operating current

■ 32-pin PLCC/LCC package

■ Jitter < 200 ps peak-to-peak (< 25 ps RMS)

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buffers

(PSCB) offer user selectable control over system clock functions.

These multiple output clock drivers provide the system integrator

with functions necessary to optimize the timing of high perfor-

mance computer systems. Each of the eight individual drivers,

arranged in four pairs of user controllable outputs, can drive

terminated transmission lines with impedances as low as 50Ω.

They can deliver minimal and specified output skews and full

swing logic levels (CY7B991 TTL or CY7B992 CMOS).

Each output is hardwired to one of the nine delay or function

configurations. Delay increments of 0.7 to 1.5 ns are determined

by the operating frequency with outputs that skew up to ±6 time

units from their nominal “zero” skew position. The completely

integrated PLL allows cancellation of external load and trans-

mission line delay effects. When this “zero delay” capability of the

PSCB is combined with the selectable output skew functions,

you can create output-to-output delays of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems.

When combined with the internal PLL, these divide functions

enable distribution of a low frequency clock that are multiplied by

two or four at the clock destination. This facility minimizes clock

distribution difficulty, allowing maximum system clock speed and

flexibility.

Logic Block Diagram

TEST

REF

VCO AND

TIME UNIT

GENERATOR

SELECT

INPUTS

(THREE

LEVEL)

SKEW

SELECT

MATRIX

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

FILTER

PHASE

FREQ

DET

[+] Feedback

1 2 3 4 5 6 ... 18 19

Summary of Contents

Page 1 - Logic Block Diagram

CY7B991CY7B992Programmable Skew Clock BufferCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document Nu

Page 2 - Pin Definitions

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 10 of 19Switching Characteristics Over the Operating Range[2, 13] (continued)CY7B991–7 CY7B992–7

Page 3 - Block Diagram Description

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 11 of 19AC Timing DiagramstODCVtODCVtREFREFFBQOTHER QINVERTED QREF DIVIDED BY 2REF DIVIDED BY 4t

Page 4 - Test Mode

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 12 of 19Operational Mode DescriptionsFigure 2 shows the PSCB configured as a zero skew clock buf

Page 5 - Operating Range

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 13 of 19the FB and REF inputs and aligns their rising edges to ensurethat all outputs have preci

Page 6 - Electrical Characteristics

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 14 of 19range since the highest frequency output is running at 20 MHz.Figure 7 shows some of the

Page 7 - AC Test Loads and Waveforms

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 15 of 19Figure 8 shows the CY7B991 and 992 connected in series to construct a zero skew clock di

Page 8

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 16 of 19Ordering InformationAccuracy(ps)Ordering Code Package TypeOperatingRange250 CY7B991–2JC

Page 9

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 17 of 19Military SpecificationsGroup A Subgroup TestingDC CharacteristicsParameter SubgroupsVOH1

Page 10 - Switching Characteristics

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 18 of 19Figure 10. 32-Pin Rectangular Leadless Chip CarrierPackage Diagrams (continued)MIL-STD-1

Page 11 - AC Timing Diagrams

Document Number: 38-07138 Rev. *B Revised June 22, 2007 Page 19 of 19PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks a

Page 12 - Operational Mode Descriptions

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 2 of 19Pin ConfigurationPin DefinitionsSignal Name IO DescriptionREF I Reference frequency input

Page 13 - [+] Feedback

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 3 of 19Block Diagram DescriptionPhase Frequency Detector and FilterThe Phase Frequency Detector

Page 14

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 4 of 19Test ModeThe TEST input is a three level input. In normal systemoperation, this pin is co

Page 15

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 5 of 19Maximum RatingsOperating outside these boundaries affects the performance andlife of the

Page 16 - Ordering Information

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 6 of 19Electrical Characteristics Over the Operating Range[6]CY7B991 CY7B992Parameter Descriptio

Page 17 - Military Specifications

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 7 of 19CapacitanceCMOS output buffer current and power dissipation specified at 50 MHz reference

Page 18 - Package Diagrams (continued)

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 8 of 19Switching Characteristics Over the Operating Range[2, 13]CY7B991–2[14]CY7B992–2[14]Parame

Page 19 - Document History

CY7B991CY7B992Document Number: 38-07138 Rev. *B Page 9 of 19Switching Characteristics Over the Operating Range[2, 13] (continued)CY7B991–5 CY7B992–5P

Related models: CY7B992

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Cypress CY7B991 User Manual

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Summary of Contents

Related models: CY7B992

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