Cypress EZ-USB Series 2100 Service Manual Page 231
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Page 12-38 Chapter 12. EZ-USB Registers EZ-USB TRM v1.9
Figure 12-31. USB Control and Status Registers
Bit 7: WAKESRC Wakeup source
This bit indicates that a high to low transaction was detected on the WAKEUP# pin. Writ-
ing a “1” to this bit resets it to “0.”
Bit 3: DISCON Signal a Disconnect on the DISCON# pin
The EZ-USB DISCON# pin reflects the complement of this bit. This bit is normally set to
0 so that the action of the DISCOE bit (below) either floats the DISCON# pin or drives it
HI.
Bit 2: DISCOE Disconnect Output Enable
DISCOE controls the output buffer on the DISCON# pin. When DISCOE=0, the pin
floats, and when DISCOE=1, it drives to the complement of the DISCON bit (above).
DISCOE is used in conjunction with the RENUM bit to perform ReNumeration(Chap-
ter 5, "EZ-USB Enumeration and ReNumeration").
USBCS USB Control and Status 7FD6
b7 b6 b5 b4 b3 b2 b1 b0
WA KES R C - - - DISCON DISCOE RENUM SIGRSUME
R/W R R R R/W R/W R/W R/W
0 0 0 0 0 1 0 0
- Technical Reference 1
- Technical Support: 3
- Phone: (858) 613-7929 3
- E-mail: [email protected] 3
- Website: 3
- 1 Introducing EZ-USB 18
- Figure 1-3. USB Packets 21
- Table 1-1. USB PIDs 21
- Interface 27
- 1.20 Pin Descriptions 35
- 2 EZ-USB CPU 46
- Figure 2-1. 8051 Registers 48
- Table 2-1. EZ-USB Interrupts 49
- 2.9 SFRs 51
- 3 EZ-USB Memory 54
- Inside EZ-USB Outside EZ-USB 57
- Inside EZ-USB 60
- Outside EZ-USB 60
- 4 EZ-USB Input/Output 62
- Alternate Function Input 65
- 4.3 IO Port Registers 66
- Figure 4-5. General I 67
- CTransfer 67
- Figure 4-6. Addressing an I 68
- CPeripheral 68
- ID1 ID0 Meaning 75
- 0 0 No EEPROM detected 75
- 1 1 Not used 75
- Table 5-3. Firmware Download 80
- Table 5-4. Firmware Upload 81
- 00000100 86
- Internal Logic 87
- Field Descriptio n Value 88
- 6 EZ-USB Bulk Transfers 98
- EPnIN Interrupt, INnBSY=0 101
- (INnBC loaded) 101
- Q S R IO 0 EP2 EP1 EP0 108
- 1. Set up the jump table 114
- A15 A14 A13 A12 A11 A10 A9 A8 119
- A7 A6 A5 A4 A3 A2 A1 A0 119
- D7 D6 D5 D4 D3 D2 D1 D0 119
- 7 EZ-USB Endpoint Zero 122
- SETUP Stage 123
- DATA Stage 123
- STATUS Stage 123
- SETUPDAT 124
- Initialization 125
- Data transfer 125
- Interrupt Control 125
- from SETUPDAT. The Field 126
- Interrupt 128
- Table 7-16. Set Configuration 140
- Table 7-17. Get Configuration 140
- Table 7-20. Sync Frame 143
- Table 7-21. Firmware Download 144
- Table 7-22. Firmware Upload 144
- 8051 FIFO 146
- USB FIFO 146
- Initialization Data transfer 147
- Register 150
- 41.66 ns 157
- Figure 8-12. Fast Read Timing 158
- Figure 8-14. ISOCTL Register 160
- Figure 8-15. ZBCOUT Register 161
- 9 EZ-USB Interrupts 164
- "RESUME" 165
- Resume signal 165
- ; interrupt request 166
- 9.4 USB Signaling Interrupts 167
- Address Op-Code Hex Val ue 173
- 0043 Jump 0x02 173
- 0044 AddrH 0xHH 173
- 0045 AddrL 0xLL 173
- Instruction 174
- Figure 9-8. I 176
- 0 0 0 0 0 0 STOPIE 0 178
- EZ-USB Core 180
- 12 EZ-USB Registers 194
- 12.3 Isochronous Data FIFOs 197
- 12.4 Isochronous Byte Counts 199
- R R R R R R R/W R 201
- RV3 RV2 RV1 RV0 0 0 1 1 201
- PINSA Port A Pins 7F99 205
- PINSB Port B Pins 7F9A 205
- OUTC Port C Pins 7F98 205
- - - - - - - UART1 UART0 207
- 0 IV4 IV3 IV2 IV1 IV0 0 0 212
- * AN2122/AN2126 only 214
- 0 0 0 0 0 0 0 0 219
- - BC6 BC5 BC4 BC3 BC2 BC1 BC0 222
- - - - - - - INnBSY INnSTL 225
- - D6 D5 D4 D3 D2 D1 D0 227
- - - - - - - OUTnBSY OUTnSTL 228
- R/W R R R R/W R/W R/W R/W 231
- 0 0 0 0 0 1 0 0 231
- 0 0 0 0 0 FC10 FC9 FC8 234
- 0 FA6 FA5 FA4 FA3 FA2 FA1 FA0 235
- 0 x 0 0 0 0 0 0 236
- FWR# pulses 240
- Bit 1-0: WMOD FWR# Pulse Mode 240
- A9 A8 A7 A6 A5 A4 0 0 243
- 13 EZ-USB AC/DC Parameters 246
- 13.1.5 General Memory Timing 247
- 13.1.6 Program Memory Read 247
- 13.1.7 Data Memory Read 247
- 13.1.8 Data Memory Write 248
- 13.1.9 Fast Data Write 248
- 13.1.10 Fast Data Read 248
- A [15.0] 250
- Fast Transfer Block Diagram 251
- FRD#[00] 252
- FRD#[01] 253
- FWR#[10] 254
- FRD#[11] 255
- 14 EZ-USB Packaging 256
- 14.2 80-Pin PQFP Package 258
- Detail "A" 259
- 14.3 48-Pin TQFP Package 260
- EZ-USB v 1.9 Appendices 262
- Table of Contents 262
- List of Figures 272
- List of Tables 274
- Appendix A: 8051 Introduction 275
- 803x/805x configurations 278
- A.6.1 Serial Ports 279
- A.6.2 Timer 2 279
- A.6.3 Timed Access Protection 279
- A.6.4 Watchdog Timer 279
- 8051_cpu 281
- B.1.1 Memory Organization 282
- B.1.2 Instruction Set 283
- B.1.3 Instruction Timing 289
- B.1.4 CPU Timing 290
- B.1.6 Dual Data Pointers 291
- C.2.1 803x/805x Compatibility 298
- C.2.2 Timers 0 and 1 298
- C.2.3 Mode 0 298
- C.2.4 Mode 1 299
- C.2.5 Mode 2 302
- C.2.6 Mode 3 303
- C.2.7 Timer Rate Control 304
- C.2.8 Timer 2 305
- C.3.1 803x/805x Compatibility 310
- C.3.2 Mode 0 310
- D0 D1 D2 D3 D4 D5 D6 D7 313
- D1 D2 D3 D4 D5 D6 D7 313
- C.3.3 Mode 1 315
- C.3.4 Mode 2 320
- C.3.5 Mode 3 322
- C.3.7 Interrupt SFRs 323
- C.4.1 Interrupt Masking 329
- C.4.2 Interrupt Priorities 330
- C.4.3 Interrupt Sampling 331
- C.4.4 Interrupt Latency 332
- C.4.5 Single-Step Operation 332
- C.6.1 Idle Mode 332
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