Cypress CYDC064B16 User Manual

1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAMCYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Cypress Semiconductor Corpor

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 10 of 26IIXInput Leakage Current 1.8V 1.8V –1 1 –1 1 µA2.5V

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 11 of 26Electrical Characteristics for VCC = 2.5V Over the

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 12 of 26 Electrical Characteristics for 3.0V Over the Opera

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 13 of 267AC Test Loads and WaveformsSwitching Characteristi

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 14 of 26 tHAAddress Hold From Write End 0 0 nstSA[28]Addres

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 15 of 26Switching Characteristics for VCC = 2.5V Over the O

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 16 of 26Interrupt Timing[33]tINSINT Set Time 35 45 nstINRIN

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 17 of 26tHZWE[30, 31]R/W LOW to High Z 15 25 nstLZWE[30, 31

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 18 of 26Switching WaveformsRead Cycle No.1 (Either Port Add

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 19 of 26Write Cycle No.1: R/W Controlled Timing[41, 42, 43,

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 2 of 26 Notes: 1. A0–A11 for 4k devices; A0–A12 for 8k devi

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 20 of 26Semaphore Read After Write Timing, Either Side[49,

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 21 of 26Timing Diagram of Read with BUSY (M/S=HIGH)[53]Writ

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 22 of 26Busy Timing Diagram No.1 (CE Arbitration)Busy Timin

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 23 of 26Interrupt Timing DiagramsNotes: 55. tHA depends on

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 24 of 26Ordering Information 16k x16 1.8V Asynchronous

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 25 of 26© Cypress Semiconductor Corporation, 2006. The inf

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 26 of 26Document History PageDocument Title: CYDC256B16/CYD

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 3 of 26Pin Configurations[3, 4, 5, 6, 7]Notes: 3. A12L and

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 4 of 26Notes: 8. IRR functionality is not supported for the

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 5 of 26Functional DescriptionThe CYDC256B16, CYDC128B16, CY

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 6 of 26then the SEM pin must be asserted instead of the CE

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 7 of 26When reading a semaphore, all sixteen/eight data lin

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 8 of 26Table 3. Input Read Register Operation[16, 19]SFEN C

CYDC256B16, CYDC128B16,CYDC064B16, CYDC128B08,CYDC064B08Document #: 001-01638 Rev. *E Page 9 of 26Maximum Ratings[23](Above which the useful life may