Cypress CY7B9911V User Manual download pdf

CY7B9911V

3.3V RoboClock+™

High Speed Low Voltage Programmable Skew

Clock Buffer

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-07408 Rev. *D Revised June 20, 2007

Features

■ All output pair skew <100 ps typical (250 max)

■ 3.75 to 110 MHz output operation

■ User selectable output functions

❐ Selectable skew to 18 ns

❐ Inverted and non-inverted

❐ Operation at

⁄

and

⁄

input frequency

❐ Operation at 2x and 4x input frequency (input as low as

3.75 MHz)

■ Zero input-to-output delay

■ 50% duty cycle outputs

■ LVTTL outputs drive 50Ω terminated lines

■ Operates from a single 3.3V supply

■ Low operating current

■ 32-pin PLCC package

■ Jitter 100 ps (typical)

Functional Description

The CY7B9911V 3.3V RoboClock+™ High Speed Low

Voltage Programmable Skew Clock Buffer (LVPSCB) offers

user selectable control over system clock functions. These

multiple output clock drivers provide the system integrator with

functions necessary to optimize the timing of high perfor-

mance computer systems. Each of the eight individual drivers,

arranged in four pairs of user controllable outputs, can drive

terminated transmission lines with impedances as low as 50Ω.

They deliver minimal and specified output skews and full swing logic

levels (LVTTL).

Each output is hardwired to one of nine delay or function

configurations. Delay increments of 0.7 to 1.5 ns are deter-

mined by the operating frequency with outputs that can skew

up to ±6 time units from their nominal “zero” skew position. The

completely integrated PLL allows external load and cancels

the transmission line delay effects. When this “zero delay”

capability of the LVPSCB is combined with the selectable

output skew functions, you can create output-to-output delays

of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems.

When combined with the internal PLL, these divide functions

allow distribution of a low frequency clock that are multiplied

by two or four at the clock destination. This facility minimizes

clock distribution difficulty enabling maximum system clock

speed and flexibility.

TEST

REF

VCO AND

TIME UNIT

GENERATOR

SELECT

INPUTS

(THREE

LEVEL)

SKEW

SELECT

MATRIX

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

FILTER

PHASE

FREQ

DET

Logic Block Diagram

[+] Feedback

1 2 3 4 5 6 ... 13 14

Summary of Contents

Page 1 - Clock Buffer

CY7B9911V3.3V RoboClock+™High Speed Low Voltage Programmable SkewClock BufferCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 951

Page 2

CY7B9911V3.3V RoboClock+™Document Number: 38-07408 Rev. *D Page 10 of 14Switching Characteristics – 7 OptionOver the Operating Range[2, 11] Parameter

Page 3

CY7B9911V3.3V RoboClock+™Document Number: 38-07408 Rev. *D Page 11 of 14 AC Timing DiagramstODCVtODCVtREFREFFBQOTHERQINVERTED QREF DIVIDED BY 2REF DI

Page 4

CY7B9911V3.3V RoboClock+™Document Number: 38-07408 Rev. *D Page 12 of 14Ordering InformationAccuracy (ps) Ordering Code Package TypeOperatingRange500

Page 5

CY7B9911V3.3V RoboClock+™Document Number: 38-07408 Rev. *D Page 13 of 14Package DiagramFigure 10. 32-Pin Plastic Leaded Chip Carrier J6551-85002-*B[+

Page 6

Document Number: 38-07408 Rev. *D Revised June 20, 2007 Page 14 of 14PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks a

Page 7

CY7B9911V3.3V RoboClock+™Document Number: 38-07408 Rev. *D Page 2 of 14Pin ConfigurationPin DefinitionsSignal Name IO DescriptionREF I Reference freq

Page 8

CY7B9911V3.3V RoboClock+™Document Number: 38-07408 Rev. *D Page 3 of 14Block Diagram DescriptionPhase Frequency Detector and FilterThe Phase Frequenc

Page 9

CY7B9911V3.3V RoboClock+™Document Number: 38-07408 Rev. *D Page 4 of 14Figure 1 shows the typical outputs with FB connected to a zero skew output.[4]

Page 10 - 3.3V RoboClock+™

CY7B9911V3.3V RoboClock+™Document Number: 38-07408 Rev. *D Page 5 of 14Operational Mode DescriptionsFigure 2 shows the LVPSCB configured as a zero sk

Page 11

CY7B9911V3.3V RoboClock+™Document Number: 38-07408 Rev. *D Page 6 of 14groups, and the PLL aligns the rising edges of REF and FB, youcan create wider

Page 12

CY7B9911V3.3V RoboClock+™Document Number: 38-07408 Rev. *D Page 7 of 14frequency, while still maintaining the low skew characteristics ofthe clock dr

Page 13

CY7B9911V3.3V RoboClock+™Document Number: 38-07408 Rev. *D Page 8 of 14Maximum RatingsOperating outside these boundaries may affect the performancean

Page 14

CY7B9911V3.3V RoboClock+™Document Number: 38-07408 Rev. *D Page 9 of 14CapacitanceTested initially and after any design or process changes that may a

Comments to this Manuals

No comments

Cypress CY7B9911V User Manual

Browse online or download User Manual for Wall clocks Cypress CY7B9911V. Cypress CY7B9911V User's Manual

Summary of Contents

Comments to this Manuals

Related products and manuals for Wall clocks Cypress CY7B9911V