Cypress CY7C1019CV33 User Manual

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128K x 8 Static RAM
CY7C1019CV33
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-05130 Rev. *F Revised August 3, 2006
Features
Pin and function compatible with CY7C1019BV33
•High speed
—t
AA
= 10 ns
CMOS for optimum speed/power
Data retention at 2.0V
Center power/ground pinout
Automatic power-down when deselected
Easy memory expansion with CE
and OE options
Available in Pb-free and non Pb-free 48-ball VFBGA,
32-pin TSOP II and 400-mil SOJ package
Functional Description
The CY7C1019CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE
), an
active LOW Output Enable (OE
), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE
) and Output Enable (OE) LOW while forcing Write
Enable (WE
) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE
LOW, and WE LOW).
The CY7C1019CV33 is available in Standard 48-ball FBGA,
32-pin TSOP II and 400-mil-wide SOJ packages
14
15
Logic Block Diagram
Pin
Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
128K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
A
10
CE
A
A
16
A
9
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOJ/TSOP II
12
13
29
32
31
30
16
15
17
18
A
7
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
A
13
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
10
A
9
I/O
2
A
0
A
4
A
5
A
6
I/O
4
V
CC
I/O
5
A
8
I/O
3
WE
V
SS
A
14
V
SS
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Summary of Contents

Page 1 - 128K x 8 Static RAM

128K x 8 Static RAMCY7C1019CV33Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #: 38-05130 R

Page 2

CY7C1019CV33Document #: 38-05130 Rev. *F Page 10 of 10Document History PageDocument Title: CY7C1019CV33 128K x 8 Static RAMDocument Number: 38-05130

Page 3

CY7C1019CV33Document #: 38-05130 Rev. *F Page 2 of 10Pin Configuration[1]Selection Guide-10 -12 -15 UnitMaximum Access Time 10 12 15 nsMaximum Opera

Page 4

CY7C1019CV33Document #: 38-05130 Rev. *F Page 3 of 10Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)

Page 5

CY7C1019CV33Document #: 38-05130 Rev. *F Page 4 of 10AC Test Loads and Waveforms[4] Switching Characteristics Over the Operating Range[5] Parameter

Page 6

CY7C1019CV33Document #: 38-05130 Rev. *F Page 5 of 10 Switching WaveformsRead Cycle No. 1[11, 12]Read Cycle No. 2 (OE Controlled)[12, 13]Write Cycle

Page 7

CY7C1019CV33Document #: 38-05130 Rev. *F Page 6 of 10 Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]Write Cycle No. 3 (WE Controlle

Page 8

CY7C1019CV33Document #: 38-05130 Rev. *F Page 7 of 10 Ordering InformationSpeed (ns) Ordering CodePackage Diagram Package TypeOperating Range10 CY7C

Page 9

CY7C1019CV33Document #: 38-05130 Rev. *F Page 8 of 10Package Diagrams (continued)51-85095-**32-pin TSOP II (51-85095)[+] Feedback

Page 10 - CY7C1019CV33

CY7C1019CV33Document #: 38-05130 Rev. *F Page 9 of 10© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to chan

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