Cypress ISR 37000 CPLD User Manual download pdf (Page 12)

Ultra37000 CPLD Family

Document #: 38-03007 Rev. *E Page 12 of 64

Logic Block Diagrams (continued)

CY37384/CY37384V

LOGIC

BLOCK

AH

LOGIC

BLOCK

AI

LOGIC

BLOCK

BD

LOGIC

BLOCK

BE

LOGIC

BLOCK

BG

LOGIC

BLOCK

BL

LOGIC

BLOCK

BI

LOGIC

BLOCK

BJ

LOGIC

BLOCK

BK

LOGIC

BLOCK

AA

LOGIC

BLOCK

AB

LOGIC

BLOCK

AC

LOGIC

BLOCK

AD

LOGIC

BLOCK

AF

LOGIC

BLOCK

BF

LOGIC

BLOCK

AG

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

PIM

Input

Clock/

Input

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

I/O

0

−I/O

11

I/O

12

−I/O

23

I/O

24

−I/O

35

I/O

48

−I/O

59

I/O

60

−I/O

71

I/O

72

−I/O

83

I/O

168

−I/O

191

I/O

156

−I/O

179

I/O

144

−I/O

167

I/O

120

−I/O

143

I/O

108

−I/O

131

4

4

4

96

96

TDI

TCK

TMS

TDO

JTAG Tap

Controller

1

LOGIC

BLOCK

AJ

LOGIC

BLOCK

BC

16

16

12 I/Os

I/O

96

−I/O

119

LOGIC

BLOCK

AK

LOGIC

BLOCK

BB

16

16

12 I/Os

I/O

84

−I/O

95

LOGIC

BLOCK

AL

LOGIC

BLOCK

BA

16

16

12 I/Os

I/O

96

−I/O

107

LOGIC

BLOCK

AE

LOGIC

BLOCK

BH

16

16

12 I/Os

12 I/Os

I/O

36

−I/O

47

I/O

132

−I/O

155

36

36

36

36

36

36

36

36

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