Cypress Quad HOTLink II CYV15G0404RB User Manual

Independent Clock Quad HOTLink II™Deserializing ReclockerCYV15G0404RBCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 10 of 27DATA[7:0] LVTTL inputasynchronous, internal pull-upControl Data Bus. The DATA[7:0] bus is the i

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 11 of 27CYV15G0404RB HOTLink II OperationThe CYV15G0404RB is a highly configurable, independentclocking

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 12 of 27operates at, or near the rate of the incoming data stream fortwo primary cases: • When the inco

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 13 of 27reclocker serial drivers for a channel are in this disabled state,the associated internal reclo

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 14 of 27Latch Banks 12, 13, and 14 load values in the related latchbanks in globally. A write operation

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 15 of 27Device Configuration StrategyFollow these steps to load the configuration latches on eachchanne

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 16 of 27Table 4. Device Control Latch Configuration Table ADDR Channel Type DATA7 DATA6 DATA5 DATA4 DAT

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 17 of 27JTAG SupportThe CYV15G0404RB contains a JTAG port to allow systemlevel diagnosis of device inte

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 18 of 27Figure 2. Receive BIST State MachineReceive BISTDetected LOWMonitor DataReceived {BISTSTx, RXDx

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 19 of 27Maximum RatingsExcedding maximum ratings may shorten the device life. Userguidelines are not te

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 2 of 27Figure 1. HOTLink II™ System ConnectionsVideo Coprocessor10101010Video Coprocessor10101010Serial

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 20 of 27 Differential CML Serial Outputs: ROUTA1±, ROUTA2±, ROUTB1±, ROUTB2±, ROUTC1±, ROUTC2±, ROUTD1±

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 21 of 27 Notes14. Tested initially and after any design or process changes that may affect these parame

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 22 of 27CYV15G0404RB Device RESET Characteristics Over the Operating RangetRSTDevice RESET Pulse Width

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 23 of 27Switching Waveforms for the CYV15G0404RB HOTLink II ReceiverCYV15G0404RB HOTLink II Bus Configu

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 24 of 27Table 6. Package Coordinate Signal Allocation Ball IDSignal Name Signal TypeBall IDSignal Name

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 25 of 27B20 ROUTB2+ CML OUT E18 VCC POWER L04 GND GROUNDC01 TDI LVTTL IN PU E19 VCC POWER L17 RXDB[8] L

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 26 of 27© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to chang

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 27 of 27Document History PageDocument Title: CYV15G0404RB Independent Clock Quad HOTLink II™ Deserializ

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 3 of 27Reclocking Deserializer Path Block DiagramINA1+INA1–INA2+INA2–INSELAClock &DataRecoveryPLLSh

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 4 of 27Reclocking Deserializer Path Block Diagram (continued)= Internal SignalINC1+INC1–INC2+INC2–INSEL

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 5 of 27WRENADDR[3:0]DATA[7:0]Device Configuration and Control Block Diagram= Internal SignalRXRATE[A..D

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 6 of 27Pin Configuration (Top View)[1]Note1. NC = Do not connect.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 7 of 27Pin Configuration (Bottom View)[1]20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1AROUTB2–INB2

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 8 of 27Pin DefinitionsCYV15G0404RB Quad HOTLink II Deserializing ReclockerName IO Characteristics Signa

CYV15G0404RBDocument #: 38-02102 Rev. *C Page 9 of 27LDTDEN LVTTL Input, internal pull upLevel Detect Transition Density Enable. When LDTDEN is HIGH,