Cypress CY7C140 User Manual

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CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
1K x 8 Dual-Port Static RAM
Cypress Semiconductor Corporation 198 Champion Court San Jose
,
CA 95134-1709 408-943-2600
Document #: 38-06002 Rev. *E Revised December 09, 2008
Features
True dual-ported memory cells, which allow simultaneous
reads of the same memory location
1K x 8 organization
0.65 micron CMOS for optimum speed and power
High speed access: 15 ns
Low operating power: I
CC
= 110 mA (maximum)
Fully asynchronous operation
Automatic power down
Master CY7C130/130A/CY7C131/131A easily expands data
bus width to 16 or more bits using slave CY7C140/CY7C141
BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY
input on CY7C140/CY7C141
INT flag for port-to-port communication
Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,
52-pin TQFP
Pb-free packages available
Functional Description
The CY7C130/130A/CY7C131/131A/CY7C140
[1]
and CY7C141
are high speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/130A/ CY7C131/131A can be used as
either a standalone 8-bit dual-port static RAM or as a master
dual-port RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or multi-
processor designs.
Each port has independent control pins; chip enable (CE
), write
enable (R/W
), and output enable (OE). Two flags are provided
on each port, BUSY
and INT. BUSY signals that the port is trying
to access the same location currently being accessed by the
other port. INT is an interrupt flag indicating that data is placed
in a unique location (3FF for the left port and 3FE for the right
port). An automatic power down feature is controlled indepen-
dently on each port by the chip enable (CE
) pins.
The CY7C130/130A and CY7C140 are available in 48-pin DIP.
The CY7C131/131A and CY7C141 are available in 52-pin
PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free
PQFP.
R/W
L
BUSY
L
CE
L
OE
L
A
9L
A
0L
A
0R
A
9R
R/W
R
CE
R
OE
R
CE
R
OE
R
CE
L
OE
L
R/W
L
R/W
R
I/O
7L
I/O
0L
I/O
7R
I/O
0R
BUSY
R
INT
L
INT
R
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
[2]
[3]
[3]
Logic Block Diagram
Notes
1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.
2. CY7C130/130A/CY7C131/131A (Master): BUSY
is open drain output and requires pull-up resistor.
CY7C140/CY7C141 (Slave): BUSY
is input.
3. Open drain outputs: pull-up resistor required.
[+] Feedback
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Summary of Contents

Page 1

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C1411K x 8 Dual-Port Static RAMCypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 9513

Page 2

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 10 of 19 Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—

Page 3

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 11 of 19 Figure 10. Busy Timing Diagram No. 1 (CE Arbitration)Fi

Page 4

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 12 of 19 Figure 12. Busy Timing Diagram No. 3Switching Waveforms

Page 5

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 13 of 19 Figure 13. Interrupt Timing DiagramsSwitching Waveforms

Page 6

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 14 of 19 Typical DC and AC Characteristics1.41.00.44.0 4.5 5.0 5.

Page 7

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 15 of 19 Ordering InformationSpeed(ns)Ordering CodePackageNamePac

Page 8

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 16 of 19 35 CY7C140-35PC P25 48-Pin (600 Mil) Molded DIP Commerci

Page 9

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 17 of 19 Package Diagrams Figure 14. 48-Pin (600 Mil) Sidebraze

Page 10 - CY7C140, CY7C141

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 18 of 19 Figure 16. 48-Pin (600 Mil) Molded DIP P25Figure 17. 5

Page 11

Document #: 38-06002 Rev. *E Revised December 09, 2008 Page 19 of 19All products and company names mentioned in this document may be the trademarks o

Page 12

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 2 of 19 Pin ConfigurationsFigure 1. Pin Diagram - DIP (Top View)

Page 13

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 3 of 19 Pin DefinitionsLeft Port Right Port DescriptionCELCERChip

Page 14

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 4 of 19 Maximum Ratings[5]Exceeding maximum ratings may shorten t

Page 15

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 5 of 19 Capacitance[10]Parameter Description Test Conditions Max

Page 16

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 6 of 19 Switching Characteristics Over the Operating Range[7, 12]

Page 17

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 7 of 19 Busy/Interrupt TimingtBLABUSY LOW from Address Match 15 2

Page 18

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 8 of 19 Switching Characteristics Over the Operating Range[7,12]

Page 19

CY7C130, CY7C130ACY7C131, CY7C131ACY7C140, CY7C141Document #: 38-06002 Rev. *E Page 9 of 19 Switching Waveforms Figure 5. Read Cycle No. 1[20, 21]Fi

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