Cypress CY7C1471BV25 User Manual

72-Mbit (2M x 36/4M x 18/1M x 72)Flow-Through SRAM with NoBL™ ArchitectureCY7C1471BV25CY7C1473BV25, CY7C1475BV25Cypress Semiconductor Corporation • 19

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 10 of 30included to greatly simplify read/modify/write sequences, whichcan be

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 11 of 30Table 4. Truth Table The truth table for CY7C1471BV25, CY7C1473BV25,

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 12 of 30Table 5. Truth Table for Read/Write The read-write truth table for C

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 13 of 30IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1471BV25, CY7C1473BV25

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 14 of 30TAP RegistersRegisters are connected between the TDI and TDO balls an

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 15 of 30no guarantee as to the value that is captured. Repeatable resultsmay

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 16 of 302.5V TAP AC Test ConditionsInput pulse levels...

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 17 of 30Table 8. Identification Register DefinitionsInstruction FieldCY7C147

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 18 of 30Table 11. Boundary Scan Exit Order (2M x 36)Bit # 165-Ball ID Bit #

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 19 of 30Table 13. Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit #

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 2 of 30Logic Block Diagram – CY7C1471BV25 (2M x 36)Logic Block Diagram – CY7C

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 20 of 30Maximum RatingsExceeding maximum ratings may impair the useful life o

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 21 of 30CapacitanceTested initially and after any design or process change th

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 22 of 30Switching Characteristics Over the Operating Range. Timing reference

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 23 of 30Switching WaveformsFigure 8 shows read-write timing waveform.[19, 20,

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 24 of 30Figure 9 shows NOP, STALL and DESELECT Cycles waveform.[19, 20, 22]Fi

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 25 of 30Figure 10 shows ZZ Mode timing waveform.[23, 24]Figure 10. ZZ Mode T

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 26 of 30Ordering InformationNot all of the speed, package and temperature ran

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 27 of 30Package Diagrams Figure 11. 100-Pin Thin Plastic Quad Flatpack (14 x

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 28 of 30Figure 12. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165Package Diagram

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 29 of 30Figure 13. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167Package Diagra

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 3 of 30Logic Block Diagram – CY7C1475BV25 (1M x 72)A0, A1, ACMODECE1CE2CE3OER

Document #: 001-15013 Rev. *E Revised February 29, 2008 Page 30 of 30NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 4 of 30Pin Configurations AAAAA1A0NC/288MNC/144MVSSVDDAAAAAADQPBDQBDQBVDDQVSS

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 5 of 30Pin Configurations (continued)AAAAA1A0NC/288MNC/144MVSSVDDAAAAAAANCNC

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 6 of 30Pin Configurations (continued)165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 7 of 30Pin Configurations (continued)ABCDEFGHJKLMNPRTUVW123456789 1110DQgDQg

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 8 of 30Table 1. Pin DefinitionsName IO DescriptionA0, A1, A Input-Synchronou

CY7C1471BV25CY7C1473BV25, CY7C1475BV25Document #: 001-15013 Rev. *E Page 9 of 30Functional OverviewThe CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25are