Cypress CY7C1510KV18 User Manual download pdf

72-Mbit QDR™-II SRAM 2-Word

Burst Architecture

CY7C1510KV18, CY7C1525KV18

CY7C1512KV18, CY7C1514KV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-00436 Rev. *E Revised March 30, 2009

Features

■ Separate Independent Read and Write Data Ports

❐ Supports concurrent transactions

■ 333 MHz Clock for High Bandwidth

■ 2-word Burst on all Accesses

■ Double Data Rate (DDR) Interfaces on both Read and Write

Ports (data transferred at 666 MHz) at 333 MHz

■ Two Input Clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Single Multiplexed Address Input bus latches Address Inputs

for both Read and Write Ports

■ Separate Port Selects for Depth Expansion

■ Synchronous internally Self-timed Writes

■ QDR™-II operates with 1.5 Cycle Read Latency when DOFF

is asserted HIGH

■ Operates similar to QDR-I Device with 1 Cycle Read Latency

when DOFF

is asserted LOW

■ Available in x8, x9, x18, and x36 Configurations

■ Full Data Coherency, providing Most Current Data

■ Core V

= 1.8V (±0.1V); IO V

DDQ

= 1.4V to V

❐ Supports both 1.5V and 1.8V IO supply

■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ Variable Drive HSTL Output Buffers

■ JTAG 1149.1 Compatible Test Access Port

■ Phase Locked Loop (PLL) for Accurate Data Placement

Configurations

CY7C1510KV18 – 8M x 8

CY7C1525KV18 – 8M x 9

CY7C1512KV18 – 4M x 18

CY7C1514KV18 – 2M x 36

Functional Description

The CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and

CY7C1514KV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II architecture. QDR-II architecture consists

of two separate ports: the read port and the write port to access

the memory array. The read port has dedicated data outputs to

support read operations and the write port has dedicated data

inputs to support write operations. QDR-II architecture has

separate data inputs and data outputs to completely eliminate

the need to “turnaround” the data bus that exists with common

I/O devices. Access to each port is through a common address

bus. Addresses for read and write addresses are latched on

alternate rising edges of the input (K) clock. Accesses to the

QDR-II read and write ports are completely independent of one

another. To maximize data throughput, both read and write ports

are equipped with DDR interfaces. Each address location is

associated with two 8-bit words (CY7C1510KV18), 9-bit words

(CY7C1525KV18), 18-bit words (CY7C1512KV18), or 36-bit

words (CY7C1514KV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K

and C

), memory bandwidth is maximized while simplifying

system design by eliminating bus turnarounds.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Table 1. Selection Guide

Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 333 300 250 200 167 MHz

Maximum Operating Current x8 790 730 640 540 480 mA

x9 790 730 640 540 480

x18 810 750 650 550 490

x36 990 910 790 660 580

[+] Feedback

1 2 3 4 5 6 ... 29 30

Summary of Contents

Page 1 - Burst Architecture

72-Mbit QDR™-II SRAM 2-WordBurst ArchitectureCY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Cypress Semiconductor Corporation • 198 Champion Cour

Page 2

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 10 of 30Truth TableThe truth table for CY7C1510KV18, CY7C1

Page 3

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 11 of 30Write Cycle DescriptionsThe write cycle descriptio

Page 4

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 12 of 30IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs

Page 5

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 13 of 30IDCODEThe IDCODE instruction loads a vendor-specif

Page 6

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 14 of 30TAP Controller State DiagramThe state diagram for

Page 7

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 15 of 30TAP Controller Block DiagramTAP Electrical Charact

Page 8

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 16 of 30TAP AC Switching Characteristics Over the Operatin

Page 9

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 17 of 30Identification Register Definitions Instruction Fi

Page 10 - CY7C1512KV18, CY7C1514KV18

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 18 of 30Boundary Scan Order Bit # Bump ID Bit # Bump ID Bi

Page 11

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 19 of 30Power Up Sequence in QDR-II SRAMQDR-II SRAMs must

Page 12

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 2 of 30Logic Block Diagram (CY7C1510KV18)Logic Block Diagr

Page 13

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 20 of 30Maximum RatingsExceeding maximum ratings may impai

Page 14

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 21 of 30IDD [19]VDD Operating Supply VDD = Max,IOUT = 0 mA

Page 15

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 22 of 30CapacitanceTested initially and after any design o

Page 16 - [+] Feedback

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 23 of 30Switching Characteristics Over the Operating Range

Page 17

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 24 of 30Output TimestCOtCHQVC/C Clock Rise (or K/K in sing

Page 18

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 25 of 30Switching WaveformsFigure 5. Read/Write/Deselect

Page 19 - PLL Constraints

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 26 of 30Ordering Information The following table lists all

Page 20

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 27 of 30250 CY7C1510KV18-250BZC 51-85180 165-Ball Fine Pit

Page 21

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 28 of 30167 CY7C1510KV18-167BZC 51-85180 165-Ball Fine Pit

Page 22 - Thermal Resistance

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 29 of 30Package DiagramFigure 6. 165-Ball FBGA (13 x 15 x

Page 23

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 3 of 30Logic Block Diagram (CY7C1512KV18)Logic Block Diagr

Page 24

Document Number: 001-00436 Rev. *E Revised March 30, 2009 Page 30 of 30QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by

Page 25

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 4 of 30Pin Configuration The pin configurations for CY7C15

Page 26

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 5 of 30CY7C1512KV18 (4M x 18)1 2 3 4 5 6 7 8 9 10 11A CQ N

Page 27

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 6 of 30Pin Definitions Pin Name I/O Pin DescriptionD[x:0]I

Page 28

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 7 of 30CQ Echo Clock CQ Referenced with Respect to C. This

Page 29 - Package Diagram

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 8 of 30Functional OverviewThe CY7C1510KV18, CY7C1525KV18,

Page 30 - Document History Page

CY7C1510KV18, CY7C1525KV18CY7C1512KV18, CY7C1514KV18Document Number: 001-00436 Rev. *E Page 9 of 30Echo ClocksEcho clocks are provided on the QDR-II t

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