Cypress CY7C1020BN User Manual

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32K x 16 Static RAM
CY7C1020BN
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 001-06443 Rev. ** Revised February 1, 2006
Features
•High speed
—t
AA
= 12, 15 ns
CMOS for optimum speed/power
Low active power
825 mW (max.)
Low CMOS standby power (L version only)
2.75 mW (max.)
Automatic power-down when deselected
Independent control of upper and lower bits
Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1020BN is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE
) and Output Enable (OE) LOW while forcing the
Write Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
9
to I/O
16
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020BN is available in standard 44-pin TSOP Type
II and 400-mil-wide SOJ packages.
WE
Logic Block Diagram
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
SOJ / TSOP II
12
13
41
44
43
42
16
15
29
30
V
CC
A
15
A
14
A
13
A
12
NC
NC
A
3
OE
V
SS
A
5
I/O
16
A
2
CE
I/O
3
I/O
1
I/O
2
BHE
NC
A
1
A
0
18
17
20
19
I/O
4
27
28
25
26
22
21
23
24
NC
V
SS
I/O
7
I/O
5
I/O
6
I/O
8
A
6
A
7
BLE
V
CC
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
A
8
A
9
A
10
A
11
32K x 16
RAM Array
I/O
1
–I/O
8
ROW DECODER
A
7
A
6
A
5
A
4
A
3
A
0
COLUMN DECODER
A
9
A
10
A
11
A
12
A
13
A
14
SENSE AMPS
DATA IN DRIVERS
OE
A
2
A
1
I/O
9
–I/O
16
CE
WE
BLE
BHE
A
8
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Summary of Contents

Page 1 - 32K x 16 Static RAM

32K x 16 Static RAMCY7C1020BNCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #: 001-06443 Re

Page 2 - CY7C1020BN

CY7C1020BNDocument #: 001-06443 Rev. ** Page 2 of 8Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)St

Page 3

CY7C1020BNDocument #: 001-06443 Rev. ** Page 3 of 8AC Test Loads and WaveformsSwitching Characteristics[5] Over the Operating RangeParameter Descrip

Page 4

CY7C1020BNDocument #: 001-06443 Rev. ** Page 4 of 8Switching Waveforms Read Cycle No. 1[9, 10]Read Cycle No. 2 (OE Controlled)[10, 11]Notes: 9. Devi

Page 5

CY7C1020BNDocument #: 001-06443 Rev. ** Page 5 of 8Write Cycle No. 1 (CE Controlled)[12, 13]Write Cycle No. 2 (BLE or BHE Controlled)Notes: 12. Data

Page 6

CY7C1020BNDocument #: 001-06443 Rev. ** Page 6 of 8Write Cycle No. 3 (WE Controlled, OE LOW)Truth TableCE OE WE BLE BHE I/O1–I/O8I/O9–I/O16Mode Powe

Page 7

CY7C1020BNDocument #: 001-06443 Rev. ** Page 7 of 8© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change

Page 8

CY7C1020BNDocument #: 001-06443 Rev. ** Page 8 of 8Document History PageDocument Title: CY7C1020BN 32K x 16 Static RAMDocument #: 001-06443REV. ECN

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