Cypress CY7C1441AV33 User Manual

36-Mbit (1M x 36/2M x 18/512K x 72)Flow-Through SRAMCY7C1441AV33CY7C1443AV33,CY7C1447AV33Cypress Semiconductor Corporation • 198 Champion Court • San

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 10 of 31ZZ Mode Electrical CharacteristicsParameter Description Test Condition

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 11 of 31Partial Truth Table for Read/WriteFunction (CY7C1441AV33)[2, 7]GW BWE

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 12 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1441AV33/CY7C1443AV33/C

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 13 of 31Instruction RegisterThree-bit instructions can be serially loaded into

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 14 of 31EXTESTThe EXTEST instruction drives the preloaded data out throughthe

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 15 of 31TAP AC Switching Characteristics Over the Operating Range[9, 10]Parame

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 16 of 313.3V TAP AC Test ConditionsInput pulse levels...

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 17 of 31 Identification Register DefinitionsInstruction FieldCY7C1441AV33(1M x

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 18 of 31165-ball FBGA Boundary Scan Order[13,14]CY7C1441AV33 (1M x 36), CY7C14

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 19 of 31Maximum RatingsExceeding maximum ratings may shorten the useful life o

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 2 of 31Logic Block Diagram – CY7C1441AV33 (1M x 36)Logic Block Diagram – CY7C1

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 20 of 31CapacitanceParameter[17]Description Test Conditions100 TQFPMax.165 FBG

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 21 of 31Switching Characteristics Over the Operating Range[22, 23]ParameterDes

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 22 of 31Timing DiagramsFigure 3. Read Cycle Timing[24].tCYCtCLCLKtADHtADSADDR

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 23 of 31Figure 4. Write Cycle Timing[24, 25].Timing Diagrams (continued)tCYC

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 24 of 31Figure 5. Read/Write Cycle Timing[24, 26, 27].Timing Diagrams (contin

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 25 of 31Figure 6. ZZ Mode Timing[28, 29]Timing Diagrams (continued)tZZISUPPLY

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 26 of 31Ordering InformationNot all of the speed, package and temperature rang

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 27 of 31Package Diagrams Figure 1. 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 28 of 31Figure 2. 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)Package Diagrams

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 29 of 31Figure 3. 209-ball FBGA (14 x 22 x1.76 mm) (51-85167)Package Diagrams

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 3 of 31Logic Block Diagram – CY7C1447AV33 (512K x 72)BWDBWCBWBBWABWEGWCE1CE2CE

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 30 of 31Document History PageDocument Title: CY7C1441AV33/CY7C1443AV33/CY7C144

Document #: 38-05357 Rev. *G Revised May 09, 2008 Page 31 of 31i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporati

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 4 of 31 Pin ConfigurationsFigure 1. 100-Pin TQFP PinoutAAAAA1A0NC/72MAVSSVDDA

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 5 of 31Pin Configurations (continued)165-ball FBGA (15 x 17 x 1.4 mm) Pinout C

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 6 of 31Pin Configurations (continued)ABCDEFGHJKLMNPRTUVW123456789 1110DQGDQGDQ

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 7 of 31Pin DefinitionsName IO DescriptionA0, A1, A Input-SynchronousAddress In

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 8 of 31DQsIO-SynchronousBidirectional Data IO lines. As inputs, they feed into

CY7C1441AV33CY7C1443AV33,CY7C1447AV33Document #: 38-05357 Rev. *G Page 9 of 31Functional OverviewAll synchronous inputs pass through input registers