Cypress NoBL CY7C1371D User Manual

18-Mbit (512K x 36/1M x 18)Flow-Through SRAM with NoBL™ Architecture CY7C1371DCY7C1373DCypress Semiconductor Corporation • 198 Champion Court • San Jo

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 10 of 29Truth Table[2, 3, 4, 5, 6, 7, 8]OperationAddress Used CE1CE2CE3ZZ ADV/LD WE BWXOE CEN CLK

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 11 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1371D/CY7C1373D incorporates a serial boun

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 12 of 29instruction if the controller is placed in a reset state asdescribed in the previous sect

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 13 of 29boundary scan path when multiple devices are connectedtogether on a board.EXTEST Output B

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 14 of 29TAP AC Switching Characteristics Over the Operating Range[10, 11]Parameter Description Mi

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 15 of 293.3V TAP AC Test ConditionsInput pulse levels ...

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 16 of 29Identification Register DefinitionsInstruction FieldCY7C1371D(512K X 36)CY7C1373D(1M X 18

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 17 of 29119-Ball BGA Boundary Scan Order[13, 14]Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # B

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 18 of 29165-Ball BGA Boundary Scan Order[13, 15]Bit # Ball ID Bit # Ball ID Bit # Ball ID1 N6 31

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 19 of 29Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. These u

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 2 of 29Logic Block Diagram – CY7C1371D (512K x 36)Logic Block Diagram – CY7C1373D (1M x 18)CMODEB

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 20 of 29Capacitance[18]Parameter Description Test Conditions100 TQFPPackage119 BGAPackage165 FBGA

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 21 of 29Switching Characteristics Over the Operating Range[23, 24]Parameter Description133 MHz 10

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 22 of 29Switching WaveformsRead/Write Waveforms[25, 26, 27]WRITED(A1)123456789CLKtCYCtCLtCH10CEtC

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 23 of 29NOP, STALL AND DESELECT Cycles[25, 26, 28]Switching Waveforms (continued)READQ(A3)456 789

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 24 of 29ZZ Mode Timing[29, 30]Switching Waveforms (continued)tZZISUPPLYCLKZZtZZRECALL INPUTS(exce

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 25 of 29Ordering InformationNot all of the speed, package and temperature ranges are available. P

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 26 of 29Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-8505

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 27 of 29Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)Package Diagrams (continued)1.2720.3

CY7C1371DCY7C1373DDocument #: 38-05556 Rev. *F Page 28 of 29© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subje

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 29 of 29Document History PageDocument Title: CY7C1371D/CY7C1373D 18-Mbit (512K x 36/1 Mbit x 18)

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 3 of 29Pin Configurations 100-Pin TQFP PinoutAAAAA1A0NC/288MNC/144MVSSVDDNC/36MAAAAAADQPBDQBDQBVD

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 4 of 29100-Pin TQFP PinoutPin Configurations (continued)AAAAA1A0NC/288MNC/144MVSSVDDNC/36MAAAAAA

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 5 of 29Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNC/576MNC/1GDQPCDQCDQDDQCDQDAA

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 6 of 29Pin Configurations (continued)165-Ball FBGA PinoutCY7C1371D (512K x 36)234 5671ABCDEFGHJK

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 7 of 29Pin DefinitionsName IO DescriptionA0, A1, A Input-SynchronousAddress Inputs used to select

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 8 of 29Functional OverviewThe CY7C1371D/CY7C1373D is a synchronous flow throughburst SRAM designe

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 9 of 29details) inputs is latched into the device and the write iscomplete. Additional accesses (