Cypress NoBL CY7C1371D User Manual download pdf (Page 9)

CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *F Page 9 of 29

details) inputs is latched into the device and the write is

complete. Additional accesses (Read/Write/Deselect) can be

initiated on this cycle.

The data written during the Write operation is controlled by

signals. The CY7C1371D/CY7C1373D provides byte

write capability that is described in the truth table. Asserting

the Write Enable input (WE

) with the selected Byte Write

Select input selectively writes to only the desired bytes. Bytes

not selected during a byte write operation remains unaltered.

A synchronous self-timed write mechanism has been provided

to simplify the write operations. Byte write capability has been

included to greatly simplify Read/Modify/Write sequences,

which can be reduced to simple byte write operations.

Because the CY7C1371D/CY7C1373D is a common IO

device, data must not be driven into the device while the

outputs are active. The Output Enable (OE

) can be deasserted

HIGH before presenting data to the DQs and DQP

inputs.

Doing so tri-states the output drivers. As a safety precaution,

DQs and DQP

are automatically tri-stated during the data

portion of a write cycle, regardless of the state of OE

Burst Write Accesses

The CY7C1371D/CY7C1373D has an on-chip burst counter

that allows the user the ability to supply a single address and

conduct up to four Write operations without reasserting the

address inputs. ADV/LD

must be driven LOW to load the initial

address, as described in the Single Write Access section

above. When ADV/LD

is driven HIGH on the subsequent clock

rise, the Chip Enables (CE

, CE

, and CE

) and WE inputs are

ignored and the burst counter is incremented. The correct

inputs must be driven in each cycle of the burst write, to

write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE

, CE

, and CE

, must remain inactive

for the duration of t

ZZREC

after the ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or V

)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

DDZZ

Sleep mode standby current ZZ > V

– 0.2V 80 mA

ZZS

Device operation to ZZ ZZ > V

– 0.2V 2t

CYC

ZZREC

ZZ recovery time ZZ < 0.2V 2t

CYC

ZZI

ZZ active to sleep current This parameter is sampled 2t

CYC

RZZI

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

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Cypress NoBL CY7C1371D User Manual Page 9

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