Cypress MoBL-USB CY7C68053 User Manual

MoBL-USB™ FX2LP18 USB MicrocontrollerCY7C68053Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document

CY7C68053Document # 001-06120 Rev *F Page 10 of 393.18.2 I2C Interface Boot Load AccessAt power on reset the I2C interface boot loader loads theVID/PI

CY7C68053Document # 001-06120 Rev *F Page 11 of 39Figure 4-2. CY7C68053 56-pin VFBGA Pin Assignment - Top view12345678ABCDEFGH1A 2A 3A 4A 5A 6A 7A 8A1

CY7C68053Document # 001-06120 Rev *F Page 12 of 394.1 CY7C68053 Pin Descriptions Note9. Unused inputs must not be left floating. Tie either HIGH or LO

CY7C68053Document # 001-06120 Rev *F Page 13 of 396F PA4 orFIFOADR0I/O/Z I(PA4)Multiplexed pin whose function is selected by: IFCONFIG[1:0].PA4 is a b

CY7C68053Document # 001-06120 Rev *F Page 14 of 39PORT D8A PD0 orFD[8]I/O/Z I(PD0)Multiplexed pin whose function is selected by the IFCONFIG[1:0] and

CY7C68053Document # 001-06120 Rev *F Page 15 of 392G IFCLK I/O/Z Z Interface Clock, used for synchronously clocking data into or out of the slave FIF

CY7C68053Document # 001-06120 Rev *F Page 16 of 395.0 Register SummaryFX2LP18 register bit definitions are described in the MoBL-USB TRM in greater d

CY7C68053Document # 001-06120 Rev *F Page 17 of 39E62C 1 ECC1B2 ECC1 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 00000000 RE62D 1 ECC2B

CY7C68053Document # 001-06120 Rev *F Page 18 of 39E65E 1 EPIE Endpoint Interrupt EnablesEP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 00000000 RWE65F 1 EP

CY7C68053Document # 001-06120 Rev *F Page 19 of 39E6A1 1 EP1OUTCS Endpoint 1 OUT Control and Status0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrbE6A2 1 EP1I

CY7C68053Document # 001-06120 Rev *F Page 2 of 39Cypress Semiconductor Corporation’s MoBL-USB FX2LP18(CY7C68053) is a low-voltage (1.8 volt) version

CY7C68053Document # 001-06120 Rev *F Page 20 of 39E6CF 1 GPIFTCB2[10]GPIF Transaction Count Byte 2TC23 TC22 TC21 TC20 TC19 TC18 TC17 TC16 00000000 RWE

CY7C68053Document # 001-06120 Rev *F Page 21 of 3981 1 SP Stack Pointer D7 D6 D5 D4 D3 D2 D1 D0 00000111 RW82 1 DPL0 Data Pointer 0 L A7 A6 A5 A4 A3 A

CY7C68053Document # 001-06120 Rev *F Page 22 of 39C9 1 ReservedCA 1 RCAP2L Capture for Timer 2, auto-reload, up-counterD7 D6 D5 D4 D3 D2 D1 D0 0000000

CY7C68053Document # 001-06120 Rev *F Page 23 of 396.0 Absolute Maximum RatingsStorage Temperature ...

CY7C68053Document # 001-06120 Rev *F Page 24 of 398.0 DC Characteristics Table 8-1. DC CharacteristicsParameter Description Conditions Min. Typ. Max

CY7C68053Document # 001-06120 Rev *F Page 25 of 399.0 AC Electrical Characteristics9.1 USB TransceiverUSB 2.0-compliant in full- and high-speed modes

CY7C68053Document # 001-06120 Rev *F Page 26 of 399.3 Slave FIFO Synchronous ReadIFCLKSLRDFLAGSSLOEtSRDtRDHtOEontXFDtXFLGDATAtIFCLKN+1tOEoffNFigure 9-

CY7C68053Document # 001-06120 Rev *F Page 27 of 399.4 Slave FIFO Asynchronous ReadSLRDFLAGStRDpwltRDpwhSLOEtXFLGtXFDDATAtOEontOEoffN+1NFigure 9-3. Sla

CY7C68053Document # 001-06120 Rev *F Page 28 of 399.5 Slave FIFO Synchronous WriteZZtSFDtFDHDATAIFCLKSLWRFLAGStWRHtXFLGtIFCLKtSWRNFigure 9-4. Slave FI

CY7C68053Document # 001-06120 Rev *F Page 29 of 399.6 Slave FIFO Asynchronous Write9.7 Slave FIFO Synchronous Packet End StrobeDATAtSFDtFDHFLAGStXFDSL

CY7C68053Document # 001-06120 Rev *F Page 3 of 393.3 I2C™ BusFX2LP18 supports the I2C bus as a master only at 100-/400-KHz. SCL and SDA pins have open

CY7C68053Document # 001-06120 Rev *F Page 30 of 39There is no specific timing requirement that needs to be metfor asserting the PKTEND pin with regard

CY7C68053Document # 001-06120 Rev *F Page 31 of 399.9 Slave FIFO Output Enable 9.10 Slave FIFO Address to Flags/Data Table 9-12. Slave FIFO Output En

CY7C68053Document # 001-06120 Rev *F Page 32 of 399.11 Slave FIFO Synchronous Address 9.12 Slave FIFO Asynchronous Address Table 9-14. Slave FIFO Sy

CY7C68053Document # 001-06120 Rev *F Page 33 of 399.13 Sequence DiagramVarious sequence diagrams and examples are presented in this section.9.13.1 Sin

CY7C68053Document # 001-06120 Rev *F Page 34 of 399.13.2 Single and Burst Synchronous Write Figure 9-15 shows the timing relationship of the SLAVE FIF

CY7C68053Document # 001-06120 Rev *F Page 35 of 399.13.3 Sequence Diagram of a Single and Burst Asynchronous Read Figure 9-16 illustrates the timing r

CY7C68053Document # 001-06120 Rev *F Page 36 of 399.13.4 Sequence Diagram of a Single and Burst Asynchronous Write Figure 9-18 illustrates the timing

CY7C68053Document # 001-06120 Rev *F Page 37 of 3910.0 Ordering Information11.0 Package DiagramThe FX2LP18 is available in a 56-pin VFBGA package.Fi

CY7C68053Document # 001-06120 Rev *F Page 38 of 39© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change wi

CY7C68053Document # 001-06120 Rev *F Page 39 of 39Document History Page Document Title: CY7C68053 MoBL-USB FX2LP18 USB MicrocontrollerDocument Number:

CY7C68053Document # 001-06120 Rev *F Page 4 of 39pushes the program counter onto its stack then jumps toaddress 0x0043, where it expects to find a ‘ju

CY7C68053Document # 001-06120 Rev *F Page 5 of 393.9 Reset and WakeupThe reset and wakeup pins are described in detail in thissection.3.9.1 Reset PinT

CY7C68053Document # 001-06120 Rev *F Page 6 of 393.10 Program/Data RAMThis section describes the FX2LP18 RAM.3.10.1 SizeThe FX2LP18 has 16 kBytes of i

CY7C68053Document # 001-06120 Rev *F Page 7 of 39vertical columns of Figure 3-5. When operating in full-speedBULK mode only the first 64 bytes of each

CY7C68053Document # 001-06120 Rev *F Page 8 of 393.12.6 Default High-Speed Alternate Settings3.13 External FIFO InterfaceThe architecture, control sig

CY7C68053Document # 001-06120 Rev *F Page 9 of 393.14.1 Three Control OUT SignalsThe 56-pin package brings out three of these signals,CTL0–CTL2. The 8