Cypress HOTLink II CYV15G0104TRB User Manual

Independent Clock HOTLink II™ Serializer andReclocking DeserializerCYV15G0104TRBCypress Semiconductor Corporation • 3901 North First Street • San Jose

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 10 of 27Phase-Align BufferData from the Input Register is passed to the Phase-AlignBuffer, when the TXD

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 11 of 27INSELA input. The Serial Line Receiver inputs are differential,and can accommodate wire interco

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 12 of 27performed by an integrated PLL that tracks the frequency ofthe transitions in the incoming bit

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 13 of 27the device configuration interface. When RXPLLPDA = 0, thereceive PLL and analog circuitry of t

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 14 of 27RXPLLPDA Receive Channel Enable. The initialization value of the RXPLLPDA latch = 0. RXPLLPDA s

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 15 of 27Device Configuration StrategyThe following is a series of ordered events needed to load theconf

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 16 of 27 Receive BISTDetected LOWMonitor DataReceived {BISTSTA, RXDA[0],NoRX PLLOut of LockYes, {BISTST

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 17 of 27Maximum Ratings(Above which the useful life may be impaired. User guidelinesonly, not tested.)S

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 18 of 27 VOLCOutput LOW Voltage (VCC Referenced)100Ω differential load VCC – 1.4 VCC – 0.7 V150Ω diffe

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 19 of 27tTXCLKR [16, 17, 18, 19]TXCLKB Rise Time 0.2 1.7 nstTXCLKF [16, 17, 18, 19]TXCLKB Fall Time 0.2

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 2 of 27The CYV15G0104TRB is ideal for SMPTE applications wheredifferent data rates and serial interface

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 20 of 27tTRGHTRGCLKA HIGH Time (TRGRATEA = 1)(Half Rate) 5.9 nsTRGCLKA HIGH Time (TRGRATEA = 0)(Full Ra

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 21 of 27CYV15G0104TRB Receive PLL Characteristics Over the Operating RangetRXLOCKReceive PLL lock to in

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 22 of 27CYV15G0104TRB HOTLink II Transmitter Switching Waveforms (continued)TXCLKOBtTXCLKOTransmit Int

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 23 of 27Switching Waveforms for the CYV15G0104TRB HOTLink II ReceiverRXCLKA+RXDA[9:0]tRXDV+tRXDV–tRXCLK

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 24 of 27Table 7. Package Coordinate Signal Allocation Ball ID Signal Name Signal TypeBall ID Signal Nam

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 25 of 27C04 VCC POWER F02 NC NO CONNECT L20 GND GROUNDC05 VCC POWER F03 VCC POWER M01 NC NO CONNECTC06

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 26 of 27 HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 27 of 27Document History PageDocument Title: CYV15G0104TRB Independent Clock HOTLink II™ Serializer and

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 3 of 27INA1+INA1–INA2+INA2–INSELAClock &DataRecoveryPLLShifterLFIA10RXDA[9:0]ReceiveSignalMonitorOu

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 4 of 27Pin Configuration (Top View)[1]Note:1. NC = Do not connect.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 5 of 27Pin Configuration (Bottom View)[1]20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1ANC VCCNC VC

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 6 of 27Pin DefinitionsCYV15G0104TRB HOTLink II Serializer and Reclocking DeserializerName I/O Character

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 7 of 27BISTSTA LVTTL Output, synchronous to the RXCLKA ± outputBIST Status Output. When RXBISTA[1:0] =

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 8 of 27SPDSELASPDSELB3-Level Select[4] static control inputSerial Rate Select. The SPDSELA and SPDSELB

CYV15G0104TRBDocument #: 38-02100 Rev. *B Page 9 of 27CYV15G0104TRB HOTLink II OperationThe CYV15G0104TRB is a highly configurable, independentclockin