Cypress Perform CY7C1370D User Manual

18-Mbit (512K x 36/1M x 18) PipelinedSRAM with NoBL™ ArchitectureCY7C1370DCY7C1372DCypress Semiconductor Corporation • 198 Champion Court • San Jose,

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 10 of 28Partial Write Cycle Description[1, 2, 3, 8]Function (CY7C1370D) WE BWdBWcBWbBWaRead H X

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 11 of 28IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1370D/CY7C1372D incorporates a serial bou

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 12 of 28When the TAP controller is in the Capture-IR state, the twoleast significant bits are lo

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 13 of 28in the TAP controller, it will directly control the state of theoutput (Q-bus) pins, whe

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 14 of 283.3V TAP AC Test ConditionsInput pulse levels ...

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 15 of 28Identification Register DefinitionsInstruction Field CY7C1372D CY7C1370D DescriptionRevi

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 16 of 28119-Ball BGA Boundary Scan Order[13, 14]Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit #

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 17 of 28165-Ball BGA Boundary Scan Order[13, 15]Bit # Ball ID Bit # Ball ID Bit # Ball ID1N6 31D

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 18 of 28Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not t

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 19 of 28Note: 18. Tested initially and after any design or process change that may affect these

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 2 of 28Selection Guide250 MHz 200 MHz 167 MHz UnitMaximum Access Time 2.6 3.0 3.4 nsMaximum Oper

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 20 of 28Switching Characteristics Over the Operating Range[23, 24]Parameter Description–250 –200

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 21 of 28Switching WaveformsRead/Write/Timing[25, 26, 27]Notes: 25. For this waveform ZZ is tied

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 22 of 28Notes: 28. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 23 of 28Ordering InformationNot all of the speed, package and temperature ranges are available.

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 24 of 28250 CY7C1370D-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 25 of 28Package DiagramsNOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DOES NOT INCLUDE MO

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 26 of 28Package Diagrams (continued)1.2720.322165437LEABDCHGFKJUPNMTR12.0019.5030° TYP.2.40 MAX.

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 27 of 28© Cypress Semiconductor Corporation, 2006. The information contained herein is subject

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 28 of 28Document History PageDocument Title: CY7C1372D/CY7C1370D 18-Mbit (512K x 36/1M x 18) Pip

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 3 of 28Pin ConfigurationsAAAAA1A0VSSVDDAAAAAAVDDQVSSDQb DQb DQb VSSVDDQDQb DQb VSSNC VDDDQaDQaVD

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 4 of 28Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUDQaVDDQNC/576MNC/1GDQcDQdDQcDQdAA A

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 5 of 28Pin Configurations (continued)234 5671ABCDEFGHJKLMNPRTDONC/576MNC/1GDQPcDQcDQPdNCDQdACE1B

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 6 of 28Pin DefinitionsPin Name I/O Type Pin DescriptionA0A1AInput-SynchronousAddress Inputs used

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 7 of 28IntroductionFunctional OverviewThe CY7C1370D and CY7C1372D are synchronous-pipelinedBurst

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 8 of 28Asserting the Write Enable input (WE) with the selected ByteWrite Select (BW) input will

CY7C1370DCY7C1372DDocument #: 38-05555 Rev. *F Page 9 of 28Notes: 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip En