Cypress CY7C2561KV18 User Manual download pdf

72-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.5 Cycle Read Latency) with ODT

PRELIMINARY

CY7C2561KV18, CY7C2576KV18

CY7C2563KV18, CY7C2565KV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-15887 Rev. *E Revised April 24, 2009

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 550 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write

ports (data transferred at 1100 MHz) at 550 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-Die Termination (ODT) feature

❐ Supported for D

[x:0]

, BWS

[x:0]

, and K/K inputs

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR™-II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

■ Operates similar to QDR-I device with 1 cycle read latency

when DOFF

is asserted LOW

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency, providing most current data

■ Core V

= 1.8V± 0.1V; IO V

DDQ

= 1.4V to V

[1]

❐ Supports both 1.5V and 1.8V IO supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase Locked Loop (PLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.5 cycles:

CY7C2561KV18 – 8M x 8

CY7C2576KV18 – 8M x 9

CY7C2563KV18 – 4M x 18

CY7C2565KV18 – 2M x 36

Functional Description

The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and

CY7C2565KV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II+ architecture. Similar to QDR-II archi-

tecture, QDR-II+ architecture consists of two separate ports: the

read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR-II+ architecture has separate data inputs and

data outputs to completely eliminate the need to “turn-around”

the data bus that exists with common IO devices. Each port is

accessed through a common address bus. Addresses for read

and write addresses are latched on alternate rising edges of the

input (K) clock. Accesses to the QDR-II+ read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with four 8-bit

words (CY7C2561KV18), 9-bit words (CY7C2576KV18), 18-bit

words (CY7C2563KV18), or 36-bit words (CY7C2565KV18) that

burst sequentially into or out of the device. Because data is trans-

ferred into and out of the device on every rising edge of both input

clocks (K and K

), memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”.

These devices have an On-Die Termination feature supported

for D

[x:0]

, BWS

[x:0]

, and K/K inputs, which helps eliminate

external termination resistors, reduce cost, reduce board area,

and simplify board routing.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the K or K

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Table 1. Selection Guide

Description 550 MHz 500 MHz 450 MHz 400 MHz Unit

Maximum Operating Frequency 550 500 450 400 MHz

Maximum Operating Current x8 900 830 760 690 mA

x9 900 830 760 690

x18 920 850 780 710

x36 1310 1210 1100 1000

Note

1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support V

DDQ

= 1.4V to V

[+] Feedback

1 2 3 4 5 6 ... 28 29

Summary of Contents

Page 1 - CY7C2563KV18, CY7C2565KV18

72-Mbit QDR™-II+ SRAM 4-Word BurstArchitecture (2.5 Cycle Read Latency) with ODTPRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Cypress

Page 2

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 10 of 29Application ExampleFigure 1 shows two Q

Page 3

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 11 of 29Table 4. Write Cycle Descriptions The

Page 4

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 12 of 29Table 6. Write Cycle DescriptionsThe w

Page 5

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 13 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)

Page 6

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 14 of 29IDCODEThe IDCODE instruction loads a ve

Page 7

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 15 of 29Figure 2. TAP Controller State Diagram

Page 8

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 16 of 29Figure 3. TAP Controller Block Diagram

Page 9

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 17 of 29TAP AC Switching Characteristics Over t

Page 10

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 18 of 29Table 7. Identification Register Defin

Page 11

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 19 of 29Table 10. Boundary Scan Order Bit # Bu

Page 12

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 2 of 29Logic Block Diagram (CY7C2561KV18)Logic

Page 13

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 20 of 29Power Up Sequence in QDR-II+ SRAMQDR-II

Page 14

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 21 of 29Maximum RatingsExceeding maximum rating

Page 15

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 22 of 29ISB1Automatic Power down CurrentMax VDD

Page 16

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 23 of 29AC Test Loads and Waveforms1.25V0.25VR

Page 17 - ALL INPUT PULSES

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 24 of 29Switching Characteristics Over the Oper

Page 18

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 25 of 29Switching WaveformsRead/Write/Deselect

Page 19

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 26 of 29Ordering Information The following tabl

Page 20 - PLL Constraints

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 27 of 29450 CY7C2561KV18-450BZC 51-85180 165-Ba

Page 21

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 28 of 29Package DiagramFigure 7. 165-Ball FBGA

Page 22

Document Number: 001-15887 Rev. *E Revised April 24, 2009 Page 29 of 29QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by

Page 23 - AC Test Loads and Waveforms

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 3 of 29Logic Block Diagram (CY7C2563KV18)Logic

Page 24

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 4 of 29Pin ConfigurationThe pin configuration f

Page 25 - Switching Waveforms

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 5 of 29CY7C2563KV18 (4M x 18)1 2 3 4 5 6 7 8 9

Page 26

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 6 of 29Table 2. Pin Definitions Pin Name IO Pi

Page 27

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 7 of 29K Input Clock Positive Input Clock Input

Page 28 - 51-85180-*A

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 8 of 29Functional OverviewThe CY7C2561KV18, CY7

Page 29 - Document History Page

PRELIMINARYCY7C2561KV18, CY7C2576KV18CY7C2563KV18, CY7C2565KV18Document Number: 001-15887 Rev. *E Page 9 of 29Read access and write access must be sch

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Cypress CY7C2561KV18 User Manual

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