Cypress CY7C1231H User Manual download pdf

2-Mbit (128K x 18) Flow-Through SRAM

with NoBL™ Architecture

CY7C1231H

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-00207 Rev. *B Revised April 26, 2006

Features

• Can support up to 133-MHz bus operations with zero

wait states

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• 128K x 18 common I/O architecture

• 3.3V core power supply

• 3.3V/2.5V I/O operation

• Fast clock-to-output times

— 6.5 ns (133-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self-timed write

• Asynchronous Output Enable

• Offered in JEDEC-standard lead-free 100-pin TQFP

package

• Burst Capability—linear or interleaved burst order

• Low standby power

Functional Description

[1]

The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous

Flow-through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1231H is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to

enable consecutive Read/Write operations with data being

transferred on every clock cycle. This feature dramatically

improves the throughput of data through the SRAM, especially

in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN

) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

Write operations are controlled by the two Byte Write Select

(BW

[A:B]

) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

MODE

READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

ADV/LD

CLK

CEN

WRITE

DRIVERS

WRITE ADDRESS

A0, A1, A

SLEEP

CONTROL

Logic Block Diagram

[+] Feedback

1 2 3 4 5 6 ... 11 12

CY7C1231H 1

Summary of Contents

Page 1 - CY7C1231H

2-Mbit (128K x 18) Flow-Through SRAMwith NoBL™ ArchitectureCY7C1231HCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709

Page 2

CY7C1231HDocument #: 001-00207 Rev. *B Page 10 of 12NOP, STALL and Deselect Cycles[18, 19, 21]ZZ Mode Timing[22, 23]Notes: 21.The IGNORE CLOCK EDGE o

Page 3

CY7C1231HDocument #: 001-00207 Rev. *B Page 11 of 12© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change

Page 4

CY7C1231HDocument #: 001-00207 Rev. *B Page 12 of 12Document History PageDocument Title: CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Ar

Page 5

CY7C1231HDocument #: 001-00207 Rev. *B Page 2 of 12Selection Guide133 MHz UnitMaximum Access Time 6.5 nsMaximum Operating Current 225 mAMaximum CMOS

Page 6

CY7C1231HDocument #: 001-00207 Rev. *B Page 3 of 12Pin Definitions Name I/O DescriptionA0, A1, A Input-SynchronousAddress Inputs used to select one o

Page 7

CY7C1231HDocument #: 001-00207 Rev. *B Page 4 of 12Functional OverviewThe CY7C1231H is a synchronous flow-through burst SRAMdesigned specifically to

Page 8

CY7C1231HDocument #: 001-00207 Rev. *B Page 5 of 12Linear Burst Address Table (MODE = GND)First AddressA1, A0SecondAddressA1, A0Third AddressA1, A0Fo

Page 9

CY7C1231HDocument #: 001-00207 Rev. *B Page 6 of 12Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Sto

Page 10

CY7C1231HDocument #: 001-00207 Rev. *B Page 7 of 12Capacitance[11]Parameter Description Test Conditions100 TQFP Max. UnitCINInput Capacitance TA = 25

Page 11

CY7C1231HDocument #: 001-00207 Rev. *B Page 8 of 12Switching Characteristics Over the Operating Range[12, 13]Parameter Description-133 UnitMin. Max.t

Page 12

CY7C1231HDocument #: 001-00207 Rev. *B Page 9 of 12Switching WaveformsRead/Write Waveforms[18, 19, 20]Notes: 18.For this waveform ZZ is tied LOW.19.W

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