Cypress Perform STK12C68 User Manual

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STK12C68
64 Kbit (8K x 8) AutoStore nvSRAM
Cypress Semiconductor Corporation 198 Champion Court San Jose
,
CA 95134-1709 408-943-2600
Document Number: 001-51027 Rev. ** Revised January 30, 2009
Features
25 ns, 35 ns, and 45 ns access times
Hands off automatic STORE on power down with external 68
µF capacitor
STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
RECALL to SRAM initiated by software or power up
Unlimited Read, Write, and Recall cycles
1,000,000 STORE cycles to QuantumTrap
100 year data retention to QuantumTrap
Single 5V+10% operation
Commercial and industrial temperatures
228-pin (330mil) SOIC, 28-pin (300mil) PDIP, 28-pin (600mil)
PDIP packages
28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages
RoHS compliance
Functional Description
The Cypress STK12C68 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB
pin.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
128 X 512
Quantum Trap
128 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
0
-
A
12
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
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Summary of Contents

Page 1 - STK12C68

STK12C6864 Kbit (8K x 8) AutoStore nvSRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600Document Number

Page 2

STK12C68Document Number: 001-51027 Rev. ** Page 10 of 20SRAM Write CycleParameterDescription25 ns 35 ns 45 ns UnitMin Max Min Max Min MaxCypressPara

Page 3

STK12C68Document Number: 001-51027 Rev. ** Page 11 of 20AutoStore or Power Up RECALLParameter Alt DescriptionSTK12C68UnitMin MaxtHRECALL [13]tRESTORE

Page 4

STK12C68Document Number: 001-51027 Rev. ** Page 12 of 20Software Controlled STORE/RECALL CycleThe software controlled STORE/RECALL cycle follows. [18]

Page 5

STK12C68Document Number: 001-51027 Rev. ** Page 13 of 20Hardware STORE CycleParameter Alt DescriptionSTK12C68UnitMin MaxtSTORE [9, 14]tHLHZ STORE Cycl

Page 6

STK12C68Document Number: 001-51027 Rev. ** Page 14 of 20Part Numbering nomenclaturePackaging Option:TR = Tape and ReelBlank = TubeSpeed:25 - 25 ns35 -

Page 7

STK12C68Document Number: 001-51027 Rev. ** Page 15 of 2045 STK12C68-SF45TR 001-85058 28-pin SOIC (330 mil) CommercialSTK12C68-SF45 001-85058 28-pin SO

Page 8

STK12C68Document Number: 001-51027 Rev. ** Page 16 of 20Package DiagramsFigure 14. 28-Pin (330 Mil) SOIC (51-85058)Figure 15. 28-Pin (300 Mil) PDIP

Page 9

STK12C68Document Number: 001-51027 Rev. ** Page 17 of 20Figure 16. 28-Pin (600 Mil) PDIP (51-85017)Package Diagrams (continued)51-85017 *B[+] Feedbac

Page 10 - SRAM Write Cycle

STK12C68Document Number: 001-51027 Rev. ** Page 18 of 20Figure 17. 28-Pin (300 Mil) Side Braze DIL (001-51695)Package Diagrams (continued)001-51695 *

Page 11 - HRECALL

STK12C68Document Number: 001-51027 Rev. ** Page 19 of 20Figure 18. 28-Pad (350 Mil) LCC (001-51696)Package Diagrams (continued)1. ALL DIMENSION ARE I

Page 12

STK12C68Document Number: 001-51027 Rev. ** Page 2 of 20Pin ConfigurationsPin DefinitionsPin Name Alt IO Type DescriptionA0–A12Input Address Inputs. Us

Page 13

Document Number: 001-51027 Rev. ** Revised January 30, 2009 Page 20 of 20AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor

Page 14

STK12C68Document Number: 001-51027 Rev. ** Page 3 of 20Device OperationThe STK12C68 nvSRAM is made up of two functional compo-nents paired in the same

Page 15

STK12C68Document Number: 001-51027 Rev. ** Page 4 of 20Figure 3. AutoStore Inhibit ModeIf the power supply drops faster than 20 us/volt before Vccrea

Page 16

STK12C68Document Number: 001-51027 Rev. ** Page 5 of 203. Read address 0x0AAA, Valid READ4. Read address 0x1FFF, Valid READ5. Read address 0x10F0, Val

Page 17

STK12C68Document Number: 001-51027 Rev. ** Page 6 of 20Best PracticesnvSRAM products have been used effectively for over 15 years.While ease-of-use is

Page 18

STK12C68Document Number: 001-51027 Rev. ** Page 7 of 20Maximum RatingsExceeding maximum ratings may shorten the useful life of thedevice. These user g

Page 19

STK12C68Document Number: 001-51027 Rev. ** Page 8 of 20Data Retention and EnduranceParameter Description Min UnitDATARData Retention 100 YearsNVCNonvo

Page 20 - PSoC Solutions

STK12C68Document Number: 001-51027 Rev. ** Page 9 of 20AC Switching Characteristics SRAM Read CycleParameterDescription25 ns 35 ns 45 ns UnitMin Max

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