Cypress CY7C1345G User Manual

CY7C1345G4-Mbit (128K x 36) Flow Through Sync SRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Docum

CY7C1345GDocument Number: 38-05517 Rev. *E Page 10 of 20Maximum RatingsExceeding the maximum ratings may shorten the battery life ofthe device. These

CY7C1345GDocument Number: 38-05517 Rev. *E Page 11 of 20CapacitanceTested initially and after any design or process change that may affect these param

CY7C1345GDocument Number: 38-05517 Rev. *E Page 12 of 20Switching CharacteristicsOver the Operating Range [9, 10]Parameter Description–133 –100 UnitMi

CY7C1345GDocument Number: 38-05517 Rev. *E Page 13 of 20Timing Diagrams Figure 1 shows the read cycle timing. [15]Figure 1. Read Cycle TimingtCYCtCLC

CY7C1345GDocument Number: 38-05517 Rev. *E Page 14 of 20Figure 2 shows the write cycle timing. [15, 16]Figure 2. Write Cycle TimingTiming Diagrams (

CY7C1345GDocument Number: 38-05517 Rev. *E Page 15 of 20Figure 3 shows the read and write timing. [16, 17, 18]Figure 3. Read/Write TimingTiming Diagr

CY7C1345GDocument Number: 38-05517 Rev. *E Page 16 of 20Figure 4 shows the ZZ mode timing. [19, 20]Figure 4. ZZ Mode Timing Timing Diagrams (continu

CY7C1345GDocument Number: 38-05517 Rev. *E Page 17 of 20Ordering InformationNot all of the speed, package and temperature ranges are available. Please

CY7C1345GDocument Number: 38-05517 Rev. *E Page 18 of 20Package Diagrams Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050NOTE

CY7C1345GDocument Number: 38-05517 Rev. *E Page 19 of 20Figure 6. 119-Ball BGA (14 x 22 x 2.4 mm), 51-85115Package Diagrams (continued)1.2720.3221654

CY7C1345GDocument Number: 38-05517 Rev. *E Page 2 of 20Logic Block DiagramADDRESSREGISTERBURSTCOUNTERAND LOGICCLRQ1Q0ENABLEREGISTERSENSEAMPSOUTPUTBUFF

Document Number: 38-05517 Rev. *E Revised July 15, 2007 Page 20 of 20Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corp

CY7C1345GDocument Number: 38-05517 Rev. *E Page 3 of 20Pin Configurations 100-Pin TQFP PinoutAAAAA1A0NC/72MNC/36MVSSVDDNC/9MAAAAAADQPBDQBVDDQVSSQDQBDQ

CY7C1345GDocument Number: 38-05517 Rev. *E Page 4 of 20119-Ball BGA PinoutPin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNC/288MNC/144MDQP

CY7C1345GDocument Number: 38-05517 Rev. *E Page 5 of 20Pin DefinitionsName IO DescriptionA0, A1, A InputSynchronousAddress Inputs Used to Select One o

CY7C1345GDocument Number: 38-05517 Rev. *E Page 6 of 20Functional OverviewAll synchronous inputs pass through input registers controlled bythe rising

CY7C1345GDocument Number: 38-05517 Rev. *E Page 7 of 20Burst SequencesThe CY7C1345G provides an on-chip two-bit wrap around burstcounter inside the SR

CY7C1345GDocument Number: 38-05517 Rev. *E Page 8 of 20Truth TableThe truth table for CY7C1345G follows. [1, 2, 3, 4, 5]Cycle DescriptionAddress UsedC

CY7C1345GDocument Number: 38-05517 Rev. *E Page 9 of 20Truth Table for Read or WriteThe partial truth table for read or write follows. [1, 6]Function