Cypress CY7C1365C User Manual download pdf

9-Mbit (256K x 32) Flow-Through Sync SRAM

CY7C1365C

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05690 Rev. *E Revised September 14, 2006

Features

• 256K x 32 common I/O

• 3.3V core power supply (V

)

• 2.5V/3.3V I/O power supply (V

DDQ

)

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Supports 3.3V I/O level

• Available in JEDEC-standard lead-free 100-Pin TQFP

package

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• “ZZ” Sleep Mode option

Functional Description

[1]

The CY7C1365C is a 256K x 32 synchronous cache RAM

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and

[2]

), Burst

Control inputs (ADSC

, ADSP, and ADV), Write Enables

(BW

[A:D], and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE

) and the ZZ pin

The CY7C1365C allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP

) or the cache Controller

Address Strobe (ADSC

) inputs. Address advancement is

controlled by the Address Advancement (ADV

) input.

Addresses and Chip Enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP

) or

Address Strobe Controller (ADSC

) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The CY7C1365C operates from a +3.3V core power supply

while all outputs may operate with either a +2.5 or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

is not available on 2 Chip Enable TQFP package.

Selection Guide

133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.5 ns

Maximum Operating Current 250 180 mA

Maximum Standby Current 40 40 mA

[+] Feedback

1 2 3 4 5 6 ... 17 18

CY7C1365C 1

Summary of Contents

Page 1 - CY7C1365C

9-Mbit (256K x 32) Flow-Through Sync SRAMCY7C1365CCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Docu

Page 2

CY7C1365CDocument #: 38-05690 Rev. *E Page 10 of 18Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Sto

Page 3

CY7C1365CDocument #: 38-05690 Rev. *E Page 11 of 18Capacitance[10]Parameter Description Test Conditions100 TQFPMax. UnitCINInput Capacitance TA = 25°

Page 4

CY7C1365CDocument #: 38-05690 Rev. *E Page 12 of 18Switching Characteristics Over the Operating Range[11, 12]Parameter Description–133 –100 UnitMin.

Page 5

CY7C1365CDocument #: 38-05690 Rev. *E Page 13 of 18Timing DiagramsRead Cycle Timing[17]Note: 17.On this diagram, when CE is LOW, CE1 is LOW, CE2 is H

Page 6

CY7C1365CDocument #: 38-05690 Rev. *E Page 14 of 18Write Cycle Timing[18, 19]Notes: 18.Full width write can be initiated by either GW LOW; or by GW H

Page 7

CY7C1365CDocument #: 38-05690 Rev. *E Page 15 of 18Read/Write Timing[17, 19, 20]Note: 20.GW is HIGH.Timing Diagrams (continued)tCYCtCLCLKtADHtADSADDR

Page 8

CY7C1365CDocument #: 38-05690 Rev. *E Page 16 of 18ZZ Mode Timing [21, 22]Ordering InformationNot all of the speed, package and temperature ranges ar

Page 9

CY7C1365CDocument #: 38-05690 Rev. *E Page 17 of 18© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change

Page 10

CY7C1365CDocument #: 38-05690 Rev. *E Page 18 of 18Document History PageDocument Title: CY7C1365C 9-Mbit (256K x 32) Flow-Through Sync SRAMDocument N

Page 11

CY7C1365CDocument #: 38-05690 Rev. *E Page 2 of 18ADDRESSREGISTERBURSTCOUNTERAND LOGICCLRQ1Q0ENABLEREGISTERSENSEAMPSOUTPUTBUFFERSINPUTREGISTERSMEMORY

Page 12

CY7C1365CDocument #: 38-05690 Rev. *E Page 3 of 18Pin Configurations 100-Pin TQFP Pinout (2 Chip Enable) (AJ version) AAAAA1A0NCNCVSSVDDNCAAAAAANCDQB

Page 13

CY7C1365CDocument #: 38-05690 Rev. *E Page 4 of 18100-Pin TQFP Pinout (3 Chip Enable) (A version)Pin Configurations (continued)AAAAA1A0NCNCVSSVDDAAA

Page 14

CY7C1365CDocument #: 38-05690 Rev. *E Page 5 of 18Pin Descriptions Name TQFP I/O DescriptionA0, A1, A 37,36,32,33,34,35,44,45,46,47,48,49,50,81,82,99

Page 15

CY7C1365CDocument #: 38-05690 Rev. *E Page 6 of 18VDD15,41,65, 91 Power Supply Power supply inputs to the core of the device.VSS17,40,67,90 Ground Gr

Page 16

CY7C1365CDocument #: 38-05690 Rev. *E Page 7 of 18Functional OverviewAll synchronous inputs pass through input registers controlledby the rising edge

Page 17

CY7C1365CDocument #: 38-05690 Rev. *E Page 8 of 18ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min. Max. UnitIDDZZSleep mo

Page 18

CY7C1365CDocument #: 38-05690 Rev. *E Page 9 of 18Truth Table for Read/Write[3, 4]Function GW BWE BWDBWCBWBBWARead HHXXXXRead HLHHHHWrite Byte (A, DQ

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