Cypress MoBL CY62138F User Manual

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Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 001-13194 Rev. *A Revised March 26, 2007
CY62138F MoBL
®
2-Mbit (256K x 8) Static RAM
Features
High speed: 45 ns
Wide voltage range: 4.5 V – 5.5 V
Pin compatible with CY62138V
Ultra low standby power
Typical standby current: 1 µA
Maximum standby current: 5 µA
Ultra low active power
Typical active current: 1.6 mA @ f = 1 MHz
Easy memory expansion with CE
1
, CE
2,
and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Available in Pb-free 32-pin SOIC and 32-pin TSOP II
packages
Functional Description
[1]
The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE
1
HIGH
or CE
2
LOW).
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO
0
through IO
7
) is then written into the location
specified on the address pins (A
0
through A
17
).
To read from the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and output enable (OE) LOW while forcing Write
Enable (WE
) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO
0
through IO
7
) are placed
in a high impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW).
Logic Block Diagram
A
0
IO
0
IO
7
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
SENSE AMPS
POWER
DOWN
WE
OE
A
13
A
14
A
15
A
16
ROW DECODER
COLUMN DECODER
256K x 8
ARRAY
DATA IN DRIVERS
A
10
A
11
A
17
CE
1
CE
2
A
12
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
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Summary of Contents

Page 1 - 2-Mbit (256K x 8) Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #: 001-13194 Rev. *A Revised March 26, 2007CY

Page 2

Document #: 001-13194 Rev. *A Page 10 of 10CY62138F MoBL®Document History PageDocument Title: CY62138F MoBL® 2-Mbit (256K x 8) Static RAMDocument Numb

Page 3

Document #: 001-13194 Rev. *A Page 2 of 10CY62138F MoBL®Pin Configuration [2]Product Portfolio ProductVCC Range (V)Speed (ns)Power DissipationOperatin

Page 4

Document #: 001-13194 Rev. *A Page 3 of 10CY62138F MoBL®Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. These user g

Page 5

Document #: 001-13194 Rev. *A Page 4 of 10CY62138F MoBL®AC Test Loads and Waveforms Parameters 5.0V UnitR1 1800 ΩR2 990 ΩRTH639 ΩVTH1.77 VData Retenti

Page 6

Document #: 001-13194 Rev. *A Page 5 of 10CY62138F MoBL®Switching Characteristics (Over the Operating Range) [11]Parameter Description45 nsUnitMin Max

Page 7

Document #: 001-13194 Rev. *A Page 6 of 10CY62138F MoBL®Switching WaveformsRead Cycle 1 (Address transition controlled) [15, 16]Read Cycle No. 2 (OE c

Page 8

Document #: 001-13194 Rev. *A Page 7 of 10CY62138F MoBL®Write Cycle No. 2 (CE1 or CE2 controlled) [10, 14, 18, 19]Write Cycle No. 3 (WE controlled, OE

Page 9

Document #: 001-13194 Rev. *A Page 8 of 10CY62138F MoBL®Package DiagramsFigure 1. 32-pin (450 Mil) Molded SOIC, 51-850810.546[13.868]0.440[11.176]0.10

Page 10 - CY62138F MoBL

Document #: 001-13194 Rev. *A Page 9 of 10© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without not

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