Cypress CY7C1307BV25 User Manual download pdf

18-Mbit Burst of 4 Pipelined SRAM with

DR™ Architecture

CY7C1307BV25

CY7C1305BV25

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05630 Rev. *A Revised April 3, 2006

Features

• Separate independent Read and Write data ports

• Supports concurrent transactions

• 167-MHz clock for high bandwidth

• 2.5 ns Clock-to-Valid access time

• 4-Word Burst for reducing the address bus frequency

• Double Data Rate (DDR) interfaces on both Read and

Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K

) for precise DDR timing

• SRAM uses rising edges only

• Two input clocks for output data (C and C

) to minimize

clock-skew and flight-time mismatches.

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG interface

Configurations

• CY7C1305BV25 – 1M x 18

• CY7C1307BV25 – 512K x 36

Functional Description

The CY7C1305BV25/CY7C1307BV25 are 2.5V Synchronous

Pipelined SRAMs equipped with QDR architecture. QDR

architecture consists of two separate ports to access the

memory array. The Read port has dedicated Data Outputs to

support Read operations and the Write Port has dedicated

Data Inputs to support Write operations. QDR architecture has

separate data inputs and data outputs to completely eliminate

the need to “turn-around” the data bus required with common

I/O devices. Access to each port is accomplished through a

common address bus. Addresses for Read and Write

addresses are latched on alternate rising edges of the input

(K) clock. Accesses to the device’s Read and Write ports are

completely independent of one another. In order to maximize

data throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with four 18-bit words (CY7C1305BV25) and four

36-bit words (CY7C1307BV25) that burst sequentially into or

out of the device. Since data can be transferred into and out

of the device on every rising edge of both input clocks (K/K

and

C/C

) memory bandwidth is maximized while simplifying

system design by eliminating bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

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Summary of Contents

Page 1 - DR™ Architecture

18-Mbit Burst of 4 Pipelined SRAM withQDR™ ArchitectureCY7C1307BV25CY7C1305BV25Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA

Page 2

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 10 of 21is loaded into the instruction register upon power-up orwhenever the TAP controller

Page 3

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 11 of 21TAP Controller State Diagram[11]Note: 11.The 0/1 next to each state represents the

Page 4

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 12 of 21 TAP Controller Block DiagramTAP Electrical Characteristics Over the Operating Rang

Page 5

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 13 of 21Output TimestTDOVTCK Clock LOW to TDO Valid 20 nstTDOXTCK Clock LOW to TDO Invalid

Page 6

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 14 of 21Scan Register SizesRegister Name Bit SizeInstruction 3Bypass 1ID 32Boundary Scan 10

Page 7

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 15 of 21Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID0 6R 27

Page 8

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 16 of 21Maximum Ratings (Above which the useful life may be impaired.)Storage Temperature .

Page 9

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 17 of 21 Capacitance[22]Parameter Description Test Conditions Max. UnitCIN Input Capacitan

Page 10 - CY7C1305BV25

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 18 of 21Switching Characteristics Over the Operating Range[23]Cypress ParameterConsortium P

Page 11

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 19 of 21Switching Waveforms[27, 28, 29] Notes: 27.Q00 refers to output from address A0. Q01

Page 12

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 2 of 21Selection GuideCY7C1305BV25-167CY7C1307BV25-167 UnitMaximum Operating Frequency 167

Page 13

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 20 of 21© Cypress Semiconductor Corporation, 2006. The information contained herein is subj

Page 14

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 21 of 21Document History PageDocument Title: CY7C1305BV25/CY7C1307BV25 18-Mbit Burst of Fou

Page 15

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 3 of 21\ Pin Configuration165-ball FBGA (13 x 15 x 1.4 mm) PinoutCY7C1305BV25 (1M x 18)1 2

Page 16

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 4 of 21Pin Definitions Name I/O DescriptionD[x:0]Input-SynchronousData input signals, sampl

Page 17

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 5 of 21IntroductionFunctional OverviewThe CY7C1305BV25/CY7C1307BV25 are synchronouspipeline

Page 18

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 6 of 21When deselected, the write port will ignore all inputs after thepending Write operat

Page 19

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 7 of 21 Truth Table[2, 3, 4, 5, 6, 7, 8, 9]Operation K RPS WPS DQ DQ DQ DQWrite Cycle:Load

Page 20

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 8 of 21Write Cycle Descriptions (CY7C1307BV25)[2, 10]BWS0BWS1BWS2BWS3KK CommentsL L L L L-H

Page 21

CY7C1307BV25CY7C1305BV25Document #: 38-05630 Rev. *A Page 9 of 21IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs incorporate a serial boundary sca

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