Cypress NoBL CY7C1352G User Manual download pdf (Page 4)

CY7C1352G

Document #: 38-05514 Rev. *D Page 4 of 12

Functional Overview

The CY7C1352G is a synchronous-pipelined Burst SRAM

designed specifically to eliminate wait states during

Write/Read transitions. All synchronous inputs pass through

input registers controlled by the rising edge of the clock. The

clock signal is qualified with the Clock Enable input signal

(CEN

). If CEN is HIGH, the clock signal is not recognized and

all internal states are maintained. All synchronous operations

are qualified with CEN. All data outputs pass through output

registers controlled by the rising edge of the clock. Maximum

access delay from the clock rise (t

) is 2.6 ns (250-MHz

device).

Accesses can be initiated by asserting all three Chip Enables

(CE

, CE

) active at the rising edge of the clock. If Clock

Enable (CEN

) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a read or write operation, depending on

the status of the Write Enable (WE

). BW

[A:B]

can be used to

conduct byte write operations.

Write operations are qualified by the Write Enable (WE

). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD

should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN

is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, (3) the Write Enable input

signal WE

is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory core

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the input of the output register. At the rising edge

of the next clock the requested data is allowed to propagate

through the output register and onto the data bus, provided OE

is active LOW. After the first clock of the read access the output

buffers are controlled by OE

and the internal control logic. OE

must be driven LOW in order for the device to drive out the

requested data. During the second clock, a subsequent

operation (Read/Write/Deselect) can be initiated. Deselecting

the device is also pipelined. Therefore, when the SRAM is

deselected at clock rise by one of the chip enable signals, its

output will tri-state following the next clock rise.

Burst Read Accesses

The CY7C1352G has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address into the

SRAM, as described in the Single Read Access section above.

The sequence of the burst counter is determined by the MODE

input signal. A LOW input on MODE selects a linear burst

mode, a HIGH selects an interleaved burst sequence. Both

burst counters use A0 and A1 in the burst sequence, and will

wrap-around when incremented sufficiently. A HIGH input on

ADV/LD

will increment the internal burst counter regardless of

the state of chip enables inputs or WE

. WE is latched at the

beginning of a burst cycle. Therefore, the type of access (Read

or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN

is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, and (3) the write signal WE

is asserted LOW. The address presented to the address inputs

is loaded into the Address Register. The write signals are

latched into the Control Logic block.

On the subsequent clock rise the data lines are automatically

tri-stated regardless of the state of the OE

input signal. This

allows the external logic to present the data on DQs and

DQP

[A:B]

. In addition, the address for the subsequent access

(Read/Write/Deselect) is latched into the Address Register

(provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQs and

DQP[A:B] (or a subset for byte write operations, see Write

Cycle Description table for details) inputs is latched into the

device and the write is complete.

The data written during the Write operation is controlled by

[A:B]

signals. The CY7C1352G provides byte write

capability that is described in the Write Cycle Description table.

Asserting the Write Enable input (WE) with the selected Byte

Write Select (BW

[A:B]

) input will selectively write to only the

desired bytes. Bytes not selected during a byte write operation

will remain unaltered. A synchronous self-timed write

mechanism has been provided to simplify the write operations.

Byte write capability has been included in order to greatly

simplify Read/Modify/Write sequences, which can be reduced

to simple byte write operations.

Because the CY7C1352G is a common I/O device, data

should not be driven into the device while the outputs are

active. The Output Enable (OE

) can be deasserted HIGH

before presenting data to the DQs

and DQP

[A:B]

inputs. Doing

so will tri-state the output drivers. As a safety precaution, DQs

and DQP

[A:B]

are automatically tri-stated during the data

portion of a write cycle, regardless of the state of OE

Burst Write Accesses

The CY7C1352G has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Write operations without reasserting the address inputs.

ADV/LD

must be driven LOW in order to load the initial

address, as described in the Single Write Access section

above. When ADV/LD

is driven HIGH on the subsequent clock

rise, the chip enables (CE

, CE

, and CE

) and WE inputs are

ignored and the burst counter is incremented. The correct

[A:B]

inputs must be driven in each cycle of the burst write

in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE

1, CE2, and CE3, must remain inactive for

the duration of t

ZZREC after the ZZ input returns LOW.

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