Cypress NoBL CY7C1352G User Manual download pdf (Page 8)

CY7C1352G

Document #: 38-05514 Rev. *D Page 8 of 12

Switching Characteristics Over the Operating Range

[16, 17]

Parameter Description

–250 –200 –166 –133

UnitMin. Max. Min. Max. Min. Max. Min. Max.

POWER

(typical) to the first Access

[12]

1111ms

Clock

CYC

Clock Cycle Time 4.0 5.0 6.0 7.5 ns

Clock HIGH 1.7 2.0 2.5 3.0 ns

Clock LOW 1.7 2.0 2.5 3.0 ns

Output Times

Data Output Valid After CLK Rise 2.6 2.8 3.5 4.0 ns

DOH

Data Output Hold After CLK Rise 1.0 1.0 1.5 1.5 ns

CLZ

Clock to Low-Z

[13, 14, 15]

0000ns

CHZ

Clock to High-Z

[13, 14, 15]

2.6 2.8 3.5 4.0 ns

OEV

OE LOW to Output Valid 2.6 2.8 3.5 4.0 ns

OELZ

OE LOW to Output Low-Z

[13, 14, 15]

0000ns

OEHZ

OE HIGH to Output High-Z

[13, 14, 15]

2.6 2.8 3.5 4.0 ns

Set-up Times

Address Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

ALS

ADV/LD Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

WES

GW, BW

[A:B]

Set-Up Before CLK Rise 1.2 1.2 1.5 1.5 ns

CENS

CEN Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

Data Input Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

CES

Chip Enable Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns

Hold Times

Address Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

ALH

ADV/LD Hold after CLK Rise 0.3 0.5 0.5 0.5 ns

WEH

GW, BW

[A:B]

Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

CENH

CEN Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

Data Input Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

CEH

Chip Enable Hold After CLK Rise 0.3 0.5 0.5 0.5 ns

Notes:

12.This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above V

minimum initially before a read or write operation

can be initiated.

13.t

CHZ

, t

CLZ

OELZ

, and t

OEHZ

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

14.At any given voltage and temperature, t

OEHZ

is less than t

OELZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve tri-state prior to Low-Z under the same system conditions.

15.This parameter is sampled and not 100% tested.

16.Timing reference level is 1.5V when V

DDQ

= 3.3V and is 1.25V when V

DDQ

= 2.5V.

17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

[+] Feedback

1 2 3 4 5 6 7 8 9 10 11 12

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Cypress NoBL CY7C1352G User Manual Page 8

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