Cypress NoBL CY7C1371D User Manual download pdf (Page 21)

CY7C1371D

CY7C1373D

Document #: 38-05556 Rev. *F Page 21 of 29

Switching Characteristics Over the Operating Range

[23, 24]

Parameter Description

133 MHz 100 MHz

UnitMin Max Min Max

POWER

[19]

11ms

Clock

CYC

Clock Cycle Time 7.5 10 ns

Clock HIGH 2.1 2.5 ns

Clock LOW 2.1 2.5 ns

Output Times

CDV

Data Output Valid After CLK Rise 6.5 8.5 ns

DOH

Data Output Hold After CLK Rise 2.0 2.0 ns

CLZ

Clock to Low-Z

[20, 21, 22]

2.0 2.0 ns

CHZ

Clock to High-Z

[20, 21, 22]

4.0 5.0 ns

OEV

OE LOW to Output Valid 3.2 3.8 ns

OELZ

OE LOW to Output Low-Z

[20, 21, 22]

00ns

OEHZ

OE HIGH to Output High-Z

[20, 21, 22]

4.0 5.0 ns

Setup Times

Address Setup Before CLK Rise 1.5 1.5 ns

ALS

ADV/LD Setup Before CLK Rise 1.5 1.5 ns

WES

WE, BW

Setup Before CLK Rise 1.5 1.5 ns

CENS

CEN

Setup Before CLK Rise 1.5 1.5 ns

Data Input Setup Before CLK Rise 1.5 1.5 ns

CES

Chip Enable Setup Before CLK Rise 1.5 1.5 ns

Hold Times

Address Hold After CLK Rise 0.5 0.5 ns

ALH

ADV/LD Hold After CLK Rise 0.5 0.5 ns

WEH

WE, BW

Hold After CLK Rise 0.5 0.5 ns

CENH

CEN Hold After CLK Rise 0.5 0.5 ns

Data Input Hold After CLK Rise 0.5 0.5 ns

CEH

Chip Enable Hold After CLK Rise 0.5 0.5 ns

Notes:

19. This part has a voltage regulator internally; t

POWER

is the time that the power needs to be supplied above V

(minimum) initially, before a read or write operation

can be initiated.

20. t

CHZ

, t

CLZ

, t

OELZ

, and t

OEHZ

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

21. At any voltage and temperature, t

OEHZ

is less than t

OELZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same data bus.

These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve

High-Z prior to Low-Z under the same system conditions.

22. This parameter is sampled and not 100% tested.

23. Timing reference level is 1.5V when V

DDQ

= 3.3V and is 1.25V when V

DDQ

= 2.5V.

24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

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