Cypress NoBL CY7C1470BV25 User Manual download pdf (Page 21)

CY7C1470BV25

CY7C1472BV25, CY7C1474BV25

Document #: 001-15032 Rev. *D Page 21 of 29

Switching Characteristics

Over the Operating Range. Timing reference is 1.25V when V

DDQ

= 2.5V. Test conditions shown in (a) of “AC Test Loads and

Waveforms” on page 20 unless otherwise noted.

Parameter Description

–250 –200 –167

Unit

Min Max Min Max Min Max

Power

[15]

(typical) to the First Access Read or Write 1 1 1 ms

Clock

CYC

Clock Cycle Time 4.0 5.0 6.0 ns

MAX

Maximum Operating Frequency 250 200 167 MHz

Clock HIGH 2.0 2.0 2.2 ns

Clock LOW 2.0 2.0 2.2 ns

Output Times

Data Output Valid After CLK Rise 3.0 3.0 3.4 ns

OEV

OE LOW to Output Valid 3.0 3.0 3.4 ns

DOH

Data Output Hold After CLK Rise 1.3 1.3 1.5 ns

CHZ

Clock to High-Z

[16, 17, 18]

3.0 3.0 3.4 ns

CLZ

Clock to Low-Z

[16, 17, 18]

1.3 1.3 1.5 ns

EOHZ

OE HIGH to Output High-Z

[16, 17, 18]

3.0 3.0 3.4 ns

EOLZ

OE LOW to Output Low-Z

[16, 17, 18]

0 0 0 ns

Setup Times

Address Setup Before CLK Rise 1.4 1.4 1.5 ns

Data Input Setup Before CLK Rise 1.4 1.4 1.5 ns

CENS

CEN Setup Before CLK Rise 1.4 1.4 1.5 ns

WES

WE, BW

Setup Before CLK Rise 1.4 1.4 1.5 ns

ALS

ADV/LD Setup Before CLK Rise 1.4 1.4 1.5 ns

CES

Chip Select Setup 1.4 1.4 1.5 ns

Hold Times

Address Hold After CLK Rise 0.4 0.4 0.5 ns

Data Input Hold After CLK Rise 0.4 0.4 0.5 ns

CENH

CEN Hold After CLK Rise 0.4 0.4 0.5 ns

WEH

WE, BW

Hold After CLK Rise 0.4 0.4 0.5 ns

ALH

ADV/LD Hold after CLK Rise 0.4 0.4 0.5 ns

CEH

Chip Select Hold After CLK Rise 0.4 0.4 0.5 ns

Notes

15.This part has a voltage regulator internally; t

power

is the time power is supplied above V

minimum initially, before a read or write operation can be initiated.

16.t

CHZ

, t

CLZ

, t

EOLZ

, and t

EOHZ

are specified with AC test conditions shown in (b) of “AC Test Loads and Waveforms” on page 20. Transition is measured ±200 mV from

steady-state voltage.

17.At any supplied voltage and temperature, t

EOHZ

is less than t

EOLZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same data

bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve

High-Z before Low-Z under the same system conditions.

18.This parameter is sampled and not 100% tested.

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