Cypress NoBL CY7C1470BV25 User Manual download pdf (Page 8)

CY7C1470BV25

CY7C1472BV25, CY7C1474BV25

Document #: 001-15032 Rev. *D Page 8 of 29

Functional Overview

The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25

are synchronous-pipelined Burst NoBL SRAMs designed specif-

ically to eliminate wait states during read or write transitions. All

synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock signal is qualified with the

Clock Enable input signal (CEN

). If CEN is HIGH, the clock signal

is not recognized and all internal states are maintained. All

synchronous operations are qualified with CEN

. All data outputs

pass through output registers controlled by the rising edge of the

clock. Maximum access delay from the clock rise (t

) is 3.0 ns

(250-MHz device).

Accesses can be initiated by asserting all three Chip Enables

(CE

, CE

) active at the rising edge of the clock. If CEN is

active LOW and ADV/LD

is asserted LOW, the address

presented to the device is latched. The access can either be a

read or write operation, depending on the status of the Write

Enable (WE

). BW

[x]

can be used to conduct Byte Write opera-

tions.

Write operations are qualified by the Write Enable (WE

). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) simplify depth expansion. All

operations (reads, writes, and deselects) are pipelined. ADV/LD

must be driven LOW after the device is deselected to load a new

address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN

is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, (3) the input signal WE is

deasserted HIGH, and (4) ADV/LD

is asserted LOW. The

address presented to the address inputs is latched into the

Address Register and presented to the memory core and control

logic. The control logic determines that a read access is in

progress and allows the requested data to propagate to the input

of the output register. At the rising edge of the next clock the

requested data is allowed to propagate through the output

provided OE

is active LOW. After the first clock of the read

access the output buffers are controlled by OE

and the internal

control logic. OE

must be driven LOW to drive out the requested

data. During the second clock, a subsequent operation (read,

write, or deselect) can be initiated. Deselecting the device is also

pipelined. Therefore, when the SRAM is deselected at clock rise

by one of the chip enable signals, its output tri-states following

the next clock rise.

Burst Read Accesses

The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25

have an on-chip burst counter that enables the user to supply a

single address and conduct up to four reads without reasserting

the address inputs. ADV/LD

must be driven LOW to load a new

address into the SRAM, as described in the Single Read

Accesses section. The sequence of the burst counter is deter-

mined by the MODE input signal. A LOW input on MODE selects

a linear burst mode, a HIGH selects an interleaved burst

sequence. Both burst counters use A0 and A1 in the burst

sequence, and wraps around when incremented sufficiently. A

HIGH input on ADV/LD

increments the internal burst counter

regardless of the state of chip enables inputs or WE

. WE is

latched at the beginning of a burst cycle. Therefore, the type of

access (read or write) is maintained throughout the burst

sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN

is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, and (3) the signal WE is

asserted LOW. The address presented to the address inputs is

loaded into the Address Register. The write signals are latched

into the Control Logic block.

On the subsequent clock rise the data lines are automatically

tri-stated regardless of the state of the OE

input signal. This

allows the external logic to present the data on DQ

and DQP

(DQ

a,b,c,d

/DQP

a,b,c,d

for CY7C1470BV25, DQ

a,b

/DQP

a,b

for

CY7C1472BV25, and DQ

a,b,c,d,e,f,g,h

/DQP

a,b,c,d,e,f,g,h

for

CY7C1474BV25). In addition, the address for the subsequent

TMS Test Mode Select

Synchronous

TMS Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.

TCK JTAG Clock Clock Input to the JTAG Circuitry.

Power Supply Power Supply Inputs to the Core of the Device.

DDQ

IO Power Supply Power Supply for the IO Circuitry.

Ground Ground for the Device. Must be connected to ground of the system.

NC – No Connects. This pin is not connected to the die.

NC(144M,

288M,

576M, 1G)

– These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and 1G

densities.

ZZ Input-

Asynchronous

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

with data integrity preserved. For normal operation, this pin has must be LOW or left floating.

ZZ pin has an internal pull down.

Table 1. Pin Definitions (continued)

Pin Name IO Type Pin Description

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1 2 3 4 5 6 7 8 9 10 11 12 13 ... 28 29

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Cypress NoBL CY7C1470BV25 User Manual Page 8

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