Cypress NoBL CY7C1470BV25 User Manual download pdf (Page 7)

CY7C1470BV25

CY7C1472BV25, CY7C1474BV25

Document #: 001-15032 Rev. *D Page 7 of 29

Table 1. Pin Definitions

Pin Name IO Type Pin Description

Input-

Synchronous

Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the

CLK.

Input-

Synchronous

Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled

on the rising edge of CLK. BW

controls DQ

and DQP

, BW

controls DQ

and DQP

, BW

controls

and DQP

, BW

controls DQ

and DQP

, BW

controls DQ

and DQP

controls DQ

and

DQP

controls DQ

and DQP

controls DQ

and DQP

Input-

Synchronous

Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

signal must be asserted LOW to initiate a write sequence.

ADV/LD Input-

Synchronous

Advance/Load Input Used to Advance the On-Chip Address Counter or Load a New Address.

When HIGH (and CEN

is asserted LOW) the internal burst counter is advanced. When LOW, a new

address can be loaded into the device for an access. After being deselected, ADV/LD

must be driven

LOW to load a new address.

CLK Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK

is only recognized if CEN

is active LOW.

Input-

Synchronous

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

and

to select/deselect the device.

Input-

Asynchronous

Output Enable, Active LOW. Combined with the synchronous logic block inside the device to control

the direction of the IO pins. When LOW, the IO pins can behave as outputs. When deasserted HIGH,

IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write

sequence, during the first clock when emerging from a deselected state and when the device has

been deselected.

CEN

Input-

Synchronous

Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.

When deasserted HIGH the clock signal is masked. Since deasserting CEN

does not deselect the

device, CEN

can be used to extend the previous cycle when required.

IO-

Synchronous

Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified

by A

[18:0]

during the previous clock rise of the read cycle. The direction of the pins is controlled by

and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When

HIGH, DQ

–DQ

are placed in a tri-state condition. The outputs are automatically tri-stated during

the data portion of a write sequence, during the first clock when emerging from a deselected state, and

when the device is deselected, regardless of the state of OE

DQP

IO-

Synchronous

Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ

[71:0]

. During write

sequences, DQP

is controlled by BW

, DQP

is controlled by BW

, DQP

is controlled by BW

, and

DQP

is controlled by BW

, DQP

is controlled by BW

DQP

is controlled by BW

DQP

is controlled

by BW

DQP

is controlled by BW

MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

Pulled LOW selects the linear burst order. MODE must not change states during operation. When

left floating MODE defaults HIGH, to an interleaved burst order.

TDO JTAG Serial

Output

Synchronous

Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.

TDI JTAG Serial Input

Synchronous

Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.

[+] Feedback

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Cypress NoBL CY7C1470BV25 User Manual Page 7

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