Cypress CY7C1165V18 User Manual download pdf

CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

18-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.5 Cycle Read Latency)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-06582 Rev. *D Revised March 06, 2008

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 300 MHz to 400 MHz clock for high bandwidth

■ 4-word burst to reduce address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 800 MHz) at 400 MHz

■ Read latency of 2.5 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency providing most current data

■ Core V

= 1.8V ± 0.1V; IO V

DDQ

= 1.4V to V

[1]

■ Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With cycle read latency of 2.5 cycles:

CY7C1161V18 – 2M x 8

CY7C1176V18 – 2M x 9

CY7C1163V18 – 1M x 18

CY7C1165V18 – 512K x 36

Functional Description

The CY7C1161V18, CY7C1176V18, CY7C1163V18, and

CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs

equipped with QDR™-II+ architecture. QDR-II+ architecture

consists of two separate ports to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR-II+ architecture has separate data inputs and

data outputs to completely eliminate the need to turn around the

data bus that is required with common IO devices. Each port can

be accessed through a common address bus. Addresses for

read and write addresses are latched onto alternate rising edges

of the input (K) clock. Accesses to the QDR-II+ read and write

ports are completely independent of one another. In order to

maximize data throughput, both read and write ports are

equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with four 8-bit words

(CY7C1161V18), 9-bit words (CY7C1176V18), 18-bit words

(CY7C1163V18), or 36-bit words (CY7C1165V18) that burst

sequentially into or out of the device. Because data can be trans-

ferred into and out of the device on every rising edge of both input

clocks K and K

, memory bandwidth is maximized while simpli-

fying system design by eliminating bus turnarounds.

Depth expansion is accomplished with port selects for each port.

Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the or K or K

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description 400 MHz 375 MHz 333 MHz 300 MHz Unit

Maximum Operating Frequency 400 375 333 300 MHz

Maximum Operating Current 1080 1020 920 850 mA

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

[+] Feedback [+] Feedback

1 2 3 4 5 6 ... 28 29

Summary of Contents

Page 1 - CY7C1163V18, CY7C1165V18

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V1818-Mbit QDR™-II+ SRAM 4-Word BurstArchitecture (2.5 Cycle Read Latency)Cypress Semiconductor Corporati

Page 2

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 10 of 29Application ExampleFigure 1 shows four QDR-II+ used in

Page 3

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 11 of 29Write Cycle DescriptionsThe write cycle descriptions o

Page 4

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 12 of 29The write cycle descriptions of CY7C1165V18 follows.[3

Page 5

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 13 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs inc

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 14 of 29IDCODEThe IDCODE instruction causes a vendor-specific

Page 7

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 15 of 29TAP Controller State DiagramFigure 2. Tap Controller S

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 16 of 29TAP Controller Block DiagramFigure 3. Tap Controller B

Page 9

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 17 of 29TAP AC Switching CharacteristicsThe Tap AC Switching C

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 18 of 29Identification Register Definitions Instruction FieldV

Page 11

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 19 of 29Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit #

Page 12

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 2 of 29Logic Block Diagram (CY7C1161V18)Logic Block Diagram (C

Page 13

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 20 of 29Power Up Sequence in QDR-II+ SRADuring power up, when

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 21 of 29Maximum RatingsExceeding maximum ratings may impair th

Page 15

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 22 of 29CapacitanceTested initially and after any design or pr

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 23 of 29Switching CharacteristicsOver the operating range[23,

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 24 of 29DLL TimingtKC VartKC VarClock Phase Jitter – 0.20 – 0.

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 25 of 29Switching WaveformsRead/Write/Deselect SequenceFigure

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 26 of 29Ordering Information Not all of the speed, package and

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 27 of 29333 CY7C1161V18-333BZC 51-85180 165-Ball Fine Pitch Ba

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 28 of 29Package DiagramFigure 7. 165-Ball FBGA (13 x 15 x 1.4

Page 22

Document Number: 001-06582 Rev. *D Revised March 06, 2008 Page 29 of 29QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 3 of 29Logic Block Diagram (CY7C1163V18)Logic Block Diagram (C

Page 24

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 4 of 29Pin ConfigurationsCY7C1161V18 (2M x 8)165-Ball FBGA (13

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 5 of 29Pin Configurations (continued)CY7C1163V18 (1M x 18)165-

Page 26

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 6 of 29Pin DefinitionsPin Name IO Pin DescriptionD[x:0]Input-S

Page 27

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 7 of 29CQEcho Clock Synchronous Echo Clock Outputs. This is a

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CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 8 of 29Functional OverviewThe CY7C1161V18, CY7C1176V18, CY7C11

Page 29

CY7C1161V18, CY7C1176V18CY7C1163V18, CY7C1165V18Document Number: 001-06582 Rev. *D Page 9 of 29Depth ExpansionThe CY7C1163V18 has a port select input

Related models: CY7C1176V18 | CY7C1161V18 | CY7C1163V18 |

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Cypress CY7C1165V18 User Manual

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Summary of Contents

Related models: CY7C1176V18 | CY7C1161V18 | CY7C1163V18 |

Comments to this Manuals

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