Cypress enCoRe CY7C602xx User Manual

CY7C601xx, CY7C602xxenCoRe™ II Low Voltage MicrocontrollerCypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 10 of 689.2 Addressing Modes9.2.1 Source ImmediateThe result of an instruction using this addres

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 11 of 689.2.5 Destination IndexedThe result of an instruction using this addressing mode is place

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 12 of 689.2.9 Source Indirect Post IncrementThe result of an instruction using this addressing mo

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 13 of 6813 7 2 SUB A, [X+expr] C, Z 40 4 1 NOP 6D 4 1 RRC A C, Z14 7 2 SUB [expr], A C, Z

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 14 of 6811. Memory Organization11.1 Flash Program Memory OrganizationFigure 11-1. Program Memor

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 15 of 6811.2 Data Memory OrganizationThe CY7C601xx and CY7C602xx microcontrollers provide up to 2

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 16 of 68Two important variables used for all functions are KEY1 andKEY2. These variables help disc

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 17 of 6811.5.3 WriteBlock FunctionThe WriteBlock function is used to store data in Flash. Data is

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 18 of 6811.5.6 EraseAll FunctionThe EraseAll function performs a series of steps that destroy the

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 19 of 6811.6 SROM Table Read DescriptionThe Silicon IDs for enCoRe II LV devices are stored in SR

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 2 of 683. ApplicationsThe CY7C601xx and CY7C602xx are targeted for the followingapplications: PC

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 20 of 68Figure 11-3. SROM Table11.6.1 Checksum FunctionThe Checksum function calculates a 16-bit

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 21 of 6812. ClockingThe enCoRe II LV has two internal oscillators, the internal 24MHz oscillator

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 22 of 68When using the 32 kHz oscillator, the PITMRL/H is read until twoconsecutive readings match

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 23 of 68Figure 12-1. CPU Clock Block DiagramSCALE(divide by 2n, n = 0-5,7)MUXCLK_EXTCLK_24MHzCPUC

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 24 of 68Read/Write – – R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0Bit [7:6]: ReservedBit 5: No

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 25 of 6812.2.2 Interval Timer Clock (ITMRCLK)The Interval Timer Clock (ITMRCLK) is sourced from t

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 26 of 68Figure 12-2. Programmable Interval Timer Block Diagram12.2.3 Timer Capture Clock (TCAPCL

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 27 of 68Table 12-5. Timer Clock Configuration (TMRCLKCR) [0x31] [R/W]Bit # 7 6 5 4 3 2 1 0Field T

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 28 of 6812.2.4 Internal Clock Trim12.2.5 External Clock TrimTable 12-6. IOSC Trim (IOSCTR) [0x3

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 29 of 6812.2.6 LPOSC Trim12.3 CPU Clock During Sleep ModeWhen the CPU enters sleep mode the CPUC

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 3 of 686. PinoutsFigure 6-1. Package Configurations1234569111516171819202221NCP0.7TIO1/P0.6TIO0/

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 30 of 6813. ResetThe microcontroller supports two types of resets: Power on Reset (POR) and Watch

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 31 of 6813.1 Power On ResetPOR occurs every time the power to the device is switched on.POR is re

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 32 of 6814.1 Sleep SequenceThe SLEEP bit is an input into the sleep logic circuit. This circuitis

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 33 of 6814.2 Wakeup SequenceWhen asleep, the only event that wakes the system up is aninterrupt.

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 34 of 6815. Low Voltage Detect Control Table 15-1. Low Voltage Control Register (LVDCR) [0x1E3]

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 35 of 6815.1 POR Compare State15.2 ECO Trim RegisterTable 15-2. Voltage Monitor Comparators Reg

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 36 of 6816. General Purpose IO Ports16.1 Port Data Registers16.1.1 P0 Data 16.1.2 P1 DataTable

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 37 of 6816.1.3 P2 Data 16.1.4 P3 Data 16.1.5 P4 Data 16.2 GPIO Port ConfigurationAll GPIO conf

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 38 of 6816.2.4 High SinkWhen set, the output sinks up to 50 mA.When clear, the output sinks up to

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 39 of 6816.2.10 P0.1/CLKOUT Configuration16.2.11 P0.2/INT0–P0.4/INT2 ConfigurationTable 16-7. P

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 4 of 686.1 Pin AssignmentsTable 6-1. Pin Assignments48 SSOP40 PDIP28 SSOP24QSOP24SOIC24PDIPName

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 40 of 6816.2.12 P0.5/TIO0–P0.6/TIO1 Configuration16.2.13 P0.7 Configuration 16.2.14 P1.0 Config

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 41 of 6816.2.15 P1.1 Configuration16.2.16 P1.2 Configuration16.2.17 P1.3 Configuration (SSEL) T

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 42 of 6816.2.18 P1.4–P1.6 Configuration (SCLK, SMOSI, SMISO) 16.2.19 P1.7 Configuration 16.2.20

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 43 of 6816.2.21 P3 Configuration 16.2.22 P4 Configuration Table 16-18. P3 Configuration (P3CR)

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 44 of 6817. Serial Peripheral Interface (SPI)The SPI Master and Slave Interface core logic runs o

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 45 of 6817.1 SPI Data RegisterWhen an interrupt occurs to indicate to firmware that a byte of rec

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 46 of 68 Table 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHALSB First CPHA CPOL Diagram0000

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 47 of 6817.3 SPI Interface PinsThe SPI interface uses the P1.3–P1.6 pins. These pins are configur

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 48 of 6818.1.2 Time CaptureenCoRe II LV has two 8-bit captures. Each capture has a separate regis

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 49 of 68Table 18-4. Capture Interrupt Enable (TCAPINTE) [0x2B] [R/W]Bit # 7 6 5 4 3 2 1 0Field Re

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 5 of 6823 19 13 9 9 16 P0.0/CLKIN GPIO Port 0 bit 0—Configured individuallyOn CY7C601xx, optional

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 50 of 68‘18.1.3 Programmable Interval Timer Table 18-8. Timer Capture 1 Falling (TCAP1F) [0x25]

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 51 of 68 Table 18-11. Programmable Interval Timer High (PITMRH) [0x27] [R]Bit # 7 6 5 4 3 2 1 0F

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 52 of 68Figure 18-3. Timer Functional Sequence Diagram[+] Feedback [+] Feedback

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 53 of 68Figure 18-4. 16-Bit Free Running Counter Loading Timing DiagramFigure 18-5. Memory Mappe

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 54 of 6819. Interrupt ControllerThe interrupt controller and its associated registers allow theus

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 55 of 6819.2 Interrupt ProcessingThe sequence of events that occur during interrupt processing is

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 56 of 6819.4.2 Interrupt Mask RegistersThe Interrupt Mask Registers (INT_MSKx) enable the individ

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 57 of 68Table 19-6. Interrupt Mask 2 (INT_MSK2) [0xDF] [R/W]Bit # 7 6 5 4 3 2 1 0Field Reserved G

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 58 of 6819.4.3 Interrupt Vector Clear RegisterTable 19-8. Interrupt Mask 0 (INT_MSK0) [0xE0] [R

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 59 of 6820. Absolute Maximum RatingsStorage Temperature ... –40°

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 6 of 687. Register SummaryTable 7-1. enCoRe II LV Register SummaryThe XIO bit in the CPU Flags R

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 60 of 68Figure 20-1. Clock Timing20.2 AC CharacteristicsParameter Description Conditions Min Ty

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 61 of 68Figure 20-2. GPIO Timing Diagram Figure 20-3. SPI Master Timing, CPHA = 110%TR_GPIOTF_GP

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 62 of 68Figure 20-4. SPI Slave Timing, CPHA = 1Figure 20-5. SPI Master Timing, CPHA = 0 MSBTSSUL

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 63 of 68Figure 20-6. SPI Slave Timing, CPHA = 0 1 MSBTSSULSBTSHDTSCKHTSDO1SSSCK (CPOL=0)SCK (CPO

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 64 of 6823. Package DiagramsFigure 23-1. 24-Pin (300-Mil) SOIC S13Figure 23-2. 24-Pin (300-Mil)

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 65 of 68Figure 23-3. 24-Pin QSOP O241Figure 23-4. 28-Pin (5.3 mm) Shrunk Small Outline Package O

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 66 of 68Figure 23-5. 40-Pin (600-Mil) Molded DIP P17Figure 23-6. 48-Pin Shrunk Small Outline Pac

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 67 of 6824. Document History PageDocument Title: CY7C601xx, CY7C602xx enCoRe™ II Low Voltage Micr

Document 38-16016 Rev. *E Revised December 08, 2008 Page 68 of 68PSoC is a registered trademark and enCoRe is a trademark of Cypress Semiconductor Cor

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 7 of 68Note In the R/W column: b = Both Read and Writer = Read Onlyw = Write Onlyc = Read or Clear

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 8 of 688. CPU ArchitectureThis family of microcontrollers is based on a high performance,8-bit, H

CY7C601xx, CY7C602xxDocument 38-16016 Rev. *E Page 9 of 689.1.1 Accumulator Register 9.1.2 Index Register 9.1.3 Stack Pointer Register9.1.4 CPU P