18-Mbit DDR-II SRAM 4-WordBurst ArchitectureCY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Cypress Semiconductor Corporation • 198 Champion Court
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 10 of 31Application ExampleFigure 1 shows two DDR-II used
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 11 of 31Burst Address Table (CY7C1319CV18, CY7C1321CV18)Fi
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 12 of 31Write Cycle DescriptionsThe write cycle descriptio
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 13 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 14 of 31IDCODEThe IDCODE instruction loads a vendor-specif
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 15 of 31TAP Controller State DiagramThe state diagram for
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 16 of 31TAP Controller Block DiagramTAP Electrical Charact
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 17 of 31TAP AC Switching Characteristics Over the Operatin
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 18 of 31Identification Register Definitions Instruction Fi
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 19 of 31Boundary Scan Order Bit # Bump ID Bit # Bump ID Bi
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 2 of 31Logic Block Diagram (CY7C1317CV18)Logic Block Diagr
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 20 of 31Power Up Sequence in DDR-II SRAMDDR-II SRAMs must
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 21 of 31Maximum RatingsExceeding maximum ratings may impai
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 22 of 31IDD [19]VDD Operating Supply VDD = Max,IOUT = 0 mA
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 23 of 31CapacitanceTested initially and after any design o
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 24 of 31Switching CharacteristicsOver the Operating Range
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 25 of 31Output TimestCOtCHQVC/C Clock Rise (or K/K in sing
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 26 of 31Switching WaveformsFigure 5. Read/Write/Deselect
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 27 of 31Ordering Information Not all of the speed, package
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 28 of 31250 CY7C1317CV18-250BZC 51-85180 165-Ball Fine Pit
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 29 of 31167 CY7C1317CV18-167BZC 51-85180 165-Ball Fine Pit
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 3 of 31Logic Block Diagram (CY7C1319CV18)Logic Block Diagr
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 30 of 31Package DiagramFigure 6. 165-Ball FBGA (13 x 15 x
Document Number: 001-07161 Rev. *D Revised June 18, 2008 Page 31 of 31QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 4 of 31Pin Configuration The pin configuration for CY7C131
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 5 of 31CY7C1319CV18 (1M x 18)1 2 3 4 5 6 7 8 9 10 11A CQ N
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 6 of 31Pin Definitions Pin Name IO Pin DescriptionDQ[x:0]I
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 7 of 31CQ Output Clock CQ Referenced with Respect to C. Th
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 8 of 31Functional OverviewThe CY7C1317CV18, CY7C1917CV18,
CY7C1317CV18, CY7C1917CV18CY7C1319CV18, CY7C1321CV18Document Number: 001-07161 Rev. *D Page 9 of 31after the read(s), the stored data from the earlier
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