Cypress CY7C1316BV18 User Manual download pdf

18-Mbit DDR-II SRAM 2-Word

Burst Architecture

CY7C1316BV18, CY7C1916BV18

CY7C1318BV18, CY7C1320BV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-05621 Rev. *D Revised June 2, 2008

Features

■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■ 300 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

)

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1316BV18 – 2M x 8

CY7C1916BV18 – 2M x 9

CY7C1318BV18 – 1M x 18

CY7C1320BV18 – 512K x 36

Functional Description

The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and

CY7C1320BV18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a one-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K

. Read data is

driven on the rising edges of C and C

if provided, or on the rising

edge of K and K

if C/C are not provided. Each address location

is associated with two 8-bit words in the case of CY7C1316BV18

and two 9-bit words in the case of CY7C1916BV18 that burst

sequentially into or out of the device. The burst counter always

starts with a ‘0’ internally in the case of CY7C1316BV18 and

CY7C1916BV18. For CY7C1318BV18 and CY7C1320BV18,

the burst counter takes in the least significant bit of the external

address and bursts two 18-bit words (in the case of

CY7C1318BV18) of two 36-bit words (in the case of

CY7C1320BV18) sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the two

output echo clocks CQ/CQ

, eliminating the need to capture data

separately from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz

Maximum Operating Current x8 815 775 705 575 490 mA

x9 820 780 710 580 490 mA

x18 855 805 730 600 510 mA

x36 930 855 775 635 540 mA

[+] Feedback

1 2 3 4 5 6 ... 30 31

Summary of Contents

Page 1 - Burst Architecture

18-Mbit DDR-II SRAM 2-WordBurst ArchitectureCY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Cypress Semiconductor Corporation • 198 Champion Court

Page 2

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 10 of 31Truth TableThe truth table for the CY7C1316BV18, CY

Page 3

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 11 of 31Write Cycle DescriptionsThe write cycle description

Page 4

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 12 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs

Page 5

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 13 of 31IDCODEThe IDCODE instruction loads a vendor-specifi

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CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 14 of 31TAP Controller State DiagramThe state diagram for t

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CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 15 of 31TAP Controller Block DiagramTAP Electrical Characte

Page 8

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 16 of 31TAP AC Switching Characteristics Over the Operating

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CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 17 of 31Identification Register Definitions Instruction Fie

Page 10 - CY7C1318BV18, CY7C1320BV18

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 18 of 31Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit

Page 11

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 19 of 31Power Up Sequence in DDR-II SRAMDDR-II SRAMs must b

Page 12

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 2 of 31Logic Block Diagram (CY7C1316BV18)Logic Block Diagra

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CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 20 of 31Maximum RatingsExceeding maximum ratings may impair

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CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 21 of 31IDD [19]VDD Operating Supply VDD = Max,IOUT = 0 mA,

Page 15

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 22 of 31CapacitanceTested initially and after any design or

Page 16 - [+] Feedback

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 23 of 31Switching CharacteristicsOver the Operating Range [

Page 17

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 24 of 31Output TimestCOtCHQVC/C Clock Rise (or K/K in singl

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CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 25 of 31Switching WaveformsFigure 5. Read/Write/Deselect S

Page 19 - DLL Constraints

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 26 of 31Ordering Information Not all of the speed, package,

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CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 27 of 31250 CY7C1316BV18-250BZC 51-85180 165-Ball Fine Pitc

Page 21

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 28 of 31167 CY7C1316BV18-167BZC 51-85180 165-Ball Fine Pitc

Page 22 - Thermal Resistance

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 29 of 31Package DiagramFigure 6. 165-Ball FBGA (13 x 15 x 1

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CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 3 of 31Logic Block Diagram (CY7C1318BV18)Logic Block Diagra

Page 24

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 30 of 31Document History PageDocument Title: CY7C1316BV18/C

Page 25

Document Number: 38-05621 Rev. *D Revised June 2, 2008 Page 31 of 31DDR RAMs and QDR RAMs comprise a new family of products developed by Cypress, Hita

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CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 4 of 31Pin Configuration The pin configuration for CY7C1316

Page 27

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 5 of 31CY7C1318BV18 (1M x 18)1 2 3 4 5 6 7 8 9 10 11A CQ NC

Page 28

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 6 of 31Pin Definitions Pin Name IO Pin DescriptionDQ[x:0]In

Page 29 - Package Diagram

CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 7 of 31CQ Output Clock CQ Referenced with Respect to C. Thi

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CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 8 of 31Functional OverviewThe CY7C1316BV18, CY7C1916BV18, C

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CY7C1316BV18, CY7C1916BV18CY7C1318BV18, CY7C1320BV18Document Number: 38-05621 Rev. *D Page 9 of 31Programmable ImpedanceAn external resistor, RQ, must

Related models: CY7C1320BV18 | CY7C1318BV18 |

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Cypress CY7C1316BV18 User Manual

Browse online or download User Manual for Hardware Cypress CY7C1316BV18. Cypress CY7C1316BV18 User Manual

Summary of Contents

Related models: CY7C1320BV18 | CY7C1318BV18 |

Comments to this Manuals

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