2-Mbit (128K x 16) Static RAMCY62137EV30MoBL®Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document
CY62137EV30MoBL®Document #: 38-05443 Rev. *B Page 10 of 12 Package Diagrams A1A1 CORNER0.750.75Ø0.30±0.05(48X)Ø0.25 M C A BØ0.05 M CBA0.15(4X)0.21±0.
CY62137EV30MoBL®Document #: 38-05443 Rev. *B Page 11 of 12© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to
CY62137EV30MoBL®Document #: 38-05443 Rev. *B Page 12 of 12Document History PageDocument Title: CY62137EV30 MoBL® 2-Mbit (128K x 16) Static RAMDocumen
CY62137EV30MoBL®Document #: 38-05443 Rev. *B Page 2 of 12 Pin Configurations[2, 3]VFBGA (Top View) 44 TSOP II (Top View)Product Portfolio Product VCC
CY62137EV30MoBL®Document #: 38-05443 Rev. *B Page 3 of 12Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not teste
CY62137EV30MoBL®Document #: 38-05443 Rev. *B Page 4 of 12 Capacitance (for all packages)[8]Parameter Description Test Conditions Max. UnitCINIn
CY62137EV30MoBL®Document #: 38-05443 Rev. *B Page 5 of 12 Switching Characteristics Over the Operating Range[11]Parameter Description45 nsUnitMin. Ma
CY62137EV30MoBL®Document #: 38-05443 Rev. *B Page 6 of 12Switching WaveformsRead Cycle 1 (Address Transition Controlled)[15, 16]Read Cycle No. 2 (OE
CY62137EV30MoBL®Document #: 38-05443 Rev. *B Page 7 of 12Write Cycle No. 1 (WE Controlled)[14, 18, 19]Write Cycle No. 2 (CE Controlled)[14, 18, 19]No
CY62137EV30MoBL®Document #: 38-05443 Rev. *B Page 8 of 12Write Cycle No. 3 (WE Controlled, OE LOW)[19]Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[
CY62137EV30MoBL®Document #: 38-05443 Rev. *B Page 9 of 12 Truth TableCE WE OE BHE BLE Inputs/Outputs Mode PowerH X X X X High Z Deselect/Power-down S
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