Cypress CY7C1333H User Manual download pdf

PRELIMINARY

2-Mbit (64K x 32) Flow-Through SRAM

with NoBL™ Architecture

CY7C1333H

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 001-00209 Rev. ** Revised April 11, 2005

Features

• Can support up to 133-MHz bus operations with zero

wait states.

— Data is transferred on every clock.

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use

• Registered inputs for flow-through operation

• Byte Write capability

• 64K x 32 common I/O architecture

• Single 3.3V power supply

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 8.0 ns (for 100-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self-timed writes Offered in Lead-Free

• Asynchronous Output Enable

• Offered in Lead-Free JEDEC-standard 100 TQFP

package

• Burst Capability—linear or interleaved burst order

• Low standby power

Functional Description

[1]

The CY7C1333H is a 3.3V, 64K x 32 Synchronous

Flow-through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1333H is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to

enable consecutive Read/Write operations with data being

transferred on every clock cycle. This feature dramatically

improves the throughput of data through the SRAM, especially

in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN

) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

Write operations are controlled by the two Byte Write Select

(BW

[A:D]

) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

MODE

CE1

CE2

CE3

READ LOGIC

MEMORY

ARRAY

INPUT

ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

ADV/LD

WRITE

DRIVERS

WRITE ADDRESS

A0, A1, A

SLEEP

Control

Logic Block Diagram

[+] Feedback

1 2 3 4 5 6 ... 11 12

PRELIMINARY 1
CY7C1333H 1

Summary of Contents

Page 1 - CY7C1333H

PRELIMINARY2-Mbit (64K x 32) Flow-Through SRAMwith NoBL™ ArchitectureCY7C1333HCypress Semiconductor Corporation • 3901 North First Street • San Jose,

Page 2

PRELIMINARYCY7C1333HDocument #: 001-00209 Rev. ** Page 10 of 12NOP, STALL and DESELECT Cycles[18, 19, 21]ZZ Mode Timing[22, 23]Switching Waveforms (c

Page 3

PRELIMINARYCY7C1333HDocument #: 001-00209 Rev. ** Page 11 of 12© Cypress Semiconductor Corporation, 2004. The information contained herein is subject

Page 4

PRELIMINARYCY7C1333HDocument #: 001-00209 Rev. ** Page 12 of 12Document History PageDocument Title: CY7C1333H 2-Mbit (64K x 32) Flow-Through SRAM with

Page 5

PRELIMINARYCY7C1333HDocument #: 001-00209 Rev. ** Page 2 of 12 Selection GuideCY7C1333H-133 CY7C1333H-100 UnitMaximum Access Time 6.5 8.0 nsMaximum O

Page 6

PRELIMINARYCY7C1333HDocument #: 001-00209 Rev. ** Page 3 of 12Pin Definitions (100-pin TQFP Package) Name I/O DescriptionA0, A1, A Input-SynchronousAd

Page 7

PRELIMINARYCY7C1333HDocument #: 001-00209 Rev. ** Page 4 of 12Functional OverviewThe CY7C1333H is a synchronous flow-through burst SRAMdesigned specif

Page 8

PRELIMINARYCY7C1333HDocument #: 001-00209 Rev. ** Page 5 of 12 Linear Burst Address Table (MODE = GND)First AddressA1, A0SecondAddressA1, A0Third Add

Page 9

PRELIMINARYCY7C1333HDocument #: 001-00209 Rev. ** Page 6 of 12Truth Table for Read/Write[2, 3]FunctionWEBWABWBBWCBWDRead HXXXXWrite No Bytes Written L

Page 10

PRELIMINARYCY7C1333HDocument #: 001-00209 Rev. ** Page 7 of 12Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not t

Page 11

PRELIMINARYCY7C1333HDocument #: 001-00209 Rev. ** Page 8 of 12Capacitance[11]Parameter Description Test Conditions 100 TQFP Package UnitCINInput Capac

Page 12

PRELIMINARYCY7C1333HDocument #: 001-00209 Rev. ** Page 9 of 12Hold TimestAHAddress Hold after CLK Rise 0.5 0.5 nstALHADV/LD Hold after CLK Rise 0.5 0.

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